diff options
Diffstat (limited to 'src/arch/arm/tlb.cc')
-rw-r--r-- | src/arch/arm/tlb.cc | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 79eef1b8d..ac18ef1f4 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -75,7 +75,7 @@ using namespace ArmISA; TLB::TLB(const ArmTLBParams *p) : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size), - isStage2(p->is_stage2), stage2Req(false), _attr(0), + isStage2(p->is_stage2), stage2Req(false), stage2DescReq(false), _attr(0), directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL), stage2Mmu(NULL), test(nullptr), rangeMRU(1), aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false), @@ -393,6 +393,7 @@ TLB::takeOverFrom(BaseTLB *_otlb) haveLPAE = otlb->haveLPAE; directToStage2 = otlb->directToStage2; stage2Req = otlb->stage2Req; + stage2DescReq = otlb->stage2DescReq; /* Sync the stage2 MMU if they exist in both * the old CPU and the new @@ -415,6 +416,7 @@ TLB::serialize(CheckpointOut &cp) const SERIALIZE_SCALAR(haveLPAE); SERIALIZE_SCALAR(directToStage2); SERIALIZE_SCALAR(stage2Req); + SERIALIZE_SCALAR(stage2DescReq); int num_entries = size; SERIALIZE_SCALAR(num_entries); @@ -431,6 +433,7 @@ TLB::unserialize(CheckpointIn &cp) UNSERIALIZE_SCALAR(haveLPAE); UNSERIALIZE_SCALAR(directToStage2); UNSERIALIZE_SCALAR(stage2Req); + UNSERIALIZE_SCALAR(stage2DescReq); int num_entries; UNSERIALIZE_SCALAR(num_entries); @@ -1310,12 +1313,15 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) (hcr.vm && !isHyp && !isSecure && !(tranType & S1CTran) && (aarch64EL < EL2) && !(tranType & S1E1Tran)); // <--- FIX THIS HACK + stage2DescReq = isStage2 || (hcr.vm && !isHyp && !isSecure && + (aarch64EL < EL2)); directToStage2 = !isStage2 && stage2Req && !sctlr.m; } else { vmid = 0; isHyp = false; directToStage2 = false; stage2Req = false; + stage2DescReq = false; } } else { // AArch32 sctlr = tc->readMiscReg(snsBankedIndex(MISCREG_SCTLR, tc, @@ -1357,12 +1363,14 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) // compute it for every translation. stage2Req = hcr.vm && !isStage2 && !isHyp && !isSecure && !(tranType & S1CTran); + stage2DescReq = hcr.vm && !isStage2 && !isHyp && !isSecure; directToStage2 = stage2Req && !sctlr.m; } else { vmid = 0; stage2Req = false; isHyp = false; directToStage2 = false; + stage2DescReq = false; } } miscRegValid = true; @@ -1440,7 +1448,7 @@ TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Fault fault; fault = tableWalker->walk(req, tc, asid, vmid, isHyp, mode, translation, timing, functional, is_secure, - tranType, stage2Req); + tranType, stage2DescReq); // for timing mode, return and wait for table walk, if (timing || fault != NoFault) { return fault; |