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-rw-r--r--src/arch/arm/tlb.cc15
1 files changed, 13 insertions, 2 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index a48805c81..a8d78308f 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -84,8 +84,19 @@ TLB::~TLB()
delete [] table;
}
+bool
+TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
+{
+ uint32_t context_id = tc->readMiscReg(MISCREG_CONTEXTIDR);
+ TlbEntry *e = lookup(va, context_id, true);
+ if (!e)
+ return false;
+ pa = e->pAddr(va);
+ return true;
+}
+
TlbEntry*
-TLB::lookup(Addr va, uint8_t cid)
+TLB::lookup(Addr va, uint8_t cid, bool functional)
{
// XXX This should either turn into a TlbMap or add caching
@@ -97,7 +108,7 @@ TLB::lookup(Addr va, uint8_t cid)
while (retval == NULL && x < size) {
if (table[x].match(va, cid)) {
retval = &table[x];
- if (x == nlu)
+ if (x == nlu && !functional)
nextnlu();
break;