1 files changed, 24 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 037f7490e..37cf9b149 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -354,6 +354,30 @@ TLB::drainResume()
 }
 
 void
+TLB::takeOverFrom(BaseTLB *_otlb)
+{
+    TLB *otlb = dynamic_cast<TLB*>(_otlb);
+    /* Make sure we actually have a valid type */
+    if (otlb) {
+        _attr = otlb->_attr;
+        haveLPAE = otlb->haveLPAE;
+        directToStage2 = otlb->directToStage2;
+        stage2Req = otlb->stage2Req;
+        bootUncacheability = otlb->bootUncacheability;
+
+        /* Sync the stage2 MMU if they exist in both
+         * the old CPU and the new
+         */
+        if (!isStage2 &&
+            stage2Tlb && otlb->stage2Tlb) {
+            stage2Tlb->takeOverFrom(otlb->stage2Tlb);
+        }
+    } else {
+        panic("Incompatible TLB type!");
+    }
+}
+
+void
 TLB::serialize(ostream &os)
 {
     DPRINTF(Checkpoint, "Serializing Arm TLB\n");