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-rw-r--r--src/arch/arm/tlb.cc7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index ece4e5a1c..94343c1c2 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -71,9 +71,10 @@ using namespace ArmISA;
TLB::TLB(const ArmTLBParams *p)
: BaseTLB(p), table(new TlbEntry[p->size]), size(p->size),
- isStage2(p->is_stage2), tableWalker(p->walker), stage2Tlb(NULL),
- stage2Mmu(NULL), rangeMRU(1), bootUncacheability(false),
- miscRegValid(false), curTranType(NormalTran)
+ isStage2(p->is_stage2), stage2Req(false), _attr(0),
+ directToStage2(false), tableWalker(p->walker), stage2Tlb(NULL),
+ stage2Mmu(NULL), rangeMRU(1), bootUncacheability(false),
+ miscRegValid(false), curTranType(NormalTran)
{
tableWalker->setTlb(this);