diff options
Diffstat (limited to 'src/arch/arm/tlb.cc')
| -rw-r--r-- | src/arch/arm/tlb.cc | 29 |
1 files changed, 13 insertions, 16 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index f824925f2..6953090d0 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -47,6 +47,7 @@ #include "arch/arm/faults.hh" #include "arch/arm/pagetable.hh" +#include "arch/arm/system.hh" #include "arch/arm/table_walker.hh" #include "arch/arm/tlb.hh" #include "arch/arm/utility.hh" @@ -62,10 +63,6 @@ #include "sim/full_system.hh" #include "sim/process.hh" -#if FULL_SYSTEM -#include "arch/arm/system.hh" -#endif - using namespace std; using namespace ArmISA; @@ -421,14 +418,14 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, } } -#if !FULL_SYSTEM - Addr paddr; - Process *p = tc->getProcessPtr(); + if (!FullSystem) { + Addr paddr; + Process *p = tc->getProcessPtr(); - if (!p->pTable->translate(vaddr, paddr)) - return Fault(new GenericPageTableFault(vaddr)); - req->setPaddr(paddr); -#endif + if (!p->pTable->translate(vaddr, paddr)) + return Fault(new GenericPageTableFault(vaddr)); + req->setPaddr(paddr); + } return NoFault; } @@ -573,11 +570,11 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, } } -#if FULL_SYSTEM - if (!bootUncacheability && - ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) - req->setFlags(Request::UNCACHEABLE); -#endif + if (FullSystem) { + if (!bootUncacheability && + ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) + req->setFlags(Request::UNCACHEABLE); + } switch ( (dacr >> (te->domain * 2)) & 0x3) { case 0: |