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-rw-r--r--src/arch/arm/tlb.cc59
1 files changed, 33 insertions, 26 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 5f104e96d..192f01bce 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1268,35 +1268,13 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
isSecure = inSecureState(tc) &&
!(tranType & HypMode) && !(tranType & S1S2NsTran);
- const OperatingMode op_mode = (OperatingMode) (uint8_t)cpsr.mode;
- aarch64 = opModeIs64(op_mode) ||
- (opModeToEL(op_mode) == EL0 && ELIs64(tc, EL1));
+ aarch64EL = tranTypeEL(cpsr, tranType);
+ aarch64 = isStage2 ?
+ ELIs64(tc, EL2) :
+ ELIs64(tc, aarch64EL == EL0 ? EL1 : aarch64EL);
if (aarch64) { // AArch64
// determine EL we need to translate in
- switch (tranType) {
- case S1E0Tran:
- case S12E0Tran:
- aarch64EL = EL0;
- break;
- case S1E1Tran:
- case S12E1Tran:
- aarch64EL = EL1;
- break;
- case S1E2Tran:
- aarch64EL = EL2;
- break;
- case S1E3Tran:
- aarch64EL = EL3;
- break;
- case NormalTran:
- case S1CTran:
- case S1S2NsTran:
- case HypMode:
- aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el;
- break;
- }
-
switch (aarch64EL) {
case EL0:
case EL1:
@@ -1396,6 +1374,35 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType)
curTranType = tranType;
}
+ExceptionLevel
+TLB::tranTypeEL(CPSR cpsr, ArmTranslationType type)
+{
+ switch (type) {
+ case S1E0Tran:
+ case S12E0Tran:
+ return EL0;
+
+ case S1E1Tran:
+ case S12E1Tran:
+ return EL1;
+
+ case S1E2Tran:
+ return EL2;
+
+ case S1E3Tran:
+ return EL3;
+
+ case NormalTran:
+ case S1CTran:
+ case S1S2NsTran:
+ case HypMode:
+ return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
+
+ default:
+ panic("Unknown translation mode!\n");
+ }
+}
+
Fault
TLB::getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
Translation *translation, bool timing, bool functional,