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Diffstat (limited to 'src/arch/arm/tlb.cc')
| -rw-r--r-- | src/arch/arm/tlb.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index da2a34084..a70a20518 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -409,6 +409,11 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, TlbEntry *te = lookup(vaddr, context_id); if (te == NULL) { + if (req->isPrefetch()){ + //if the request is a prefetch don't attempt to fill the TLB + //or go any further with the memory access + return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss); + } // start translation table walk, pass variables rather than // re-retreaving in table walker for speed DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n", |