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Diffstat (limited to 'src/arch/arm/tlb.cc')
| -rw-r--r-- | src/arch/arm/tlb.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index e54eb25d6..4b43a50a4 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1308,7 +1308,8 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) isPriv = aarch64EL != EL0; if (haveVirtualization) { vmid = bits(tc->readMiscReg(MISCREG_VTTBR_EL2), 55, 48); - isHyp = tranType & HypMode; + isHyp = aarch64EL == EL2; + isHyp |= tranType & HypMode; isHyp &= (tranType & S1S2NsTran) == 0; isHyp &= (tranType & S1CTran) == 0; // Work out if we should skip the first stage of translation and go |