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-rw-r--r--src/arch/arm/tlb.hh14
1 files changed, 6 insertions, 8 deletions
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index f6776b0a9..1f9ec01ec 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -155,10 +155,10 @@ class TLB : public BaseTLB
virtual ~TLB();
- void takeOverFrom(BaseTLB *otlb);
+ void takeOverFrom(BaseTLB *otlb) override;
/// setup all the back pointers
- virtual void init();
+ void init() override;
TableWalker *getTableWalker() { return tableWalker; }
@@ -197,7 +197,7 @@ class TLB : public BaseTLB
/** Reset the entire TLB. Used for CPU switching to prevent stale
* translations after multiple switches
*/
- void flushAll()
+ void flushAll() override
{
flushAllSecurity(false, 0, true);
flushAllSecurity(true, 0, true);
@@ -230,14 +230,12 @@ class TLB : public BaseTLB
void printTlb() const;
- void demapPage(Addr vaddr, uint64_t asn)
+ void demapPage(Addr vaddr, uint64_t asn) override
{
// needed for x86 only
panic("demapPage() is not implemented.\n");
}
- static bool validVirtualAddress(Addr vaddr);
-
/**
* Do a functional lookup on the TLB (for debugging)
* and don't modify any internal state
@@ -290,7 +288,7 @@ class TLB : public BaseTLB
void serialize(CheckpointOut &cp) const override;
void unserialize(CheckpointIn &cp) override;
- void regStats();
+ void regStats() override;
void regProbePoints() override;
@@ -304,7 +302,7 @@ class TLB : public BaseTLB
*
* @return A pointer to the walker master port
*/
- virtual BaseMasterPort* getMasterPort();
+ BaseMasterPort* getMasterPort() override;
// Caching misc register values here.
// Writing to misc registers needs to invalidate them.