diff options
Diffstat (limited to 'src/arch/arm/tracers/tarmac_parser.cc')
| -rw-r--r-- | src/arch/arm/tracers/tarmac_parser.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc index 860bb1b0b..04a2a051e 100644 --- a/src/arch/arm/tracers/tarmac_parser.cc +++ b/src/arch/arm/tracers/tarmac_parser.cc @@ -57,7 +57,7 @@ #include "sim/sim_exit.hh" using namespace std; -using namespace TheISA; +using namespace ArmISA; namespace Trace { @@ -743,7 +743,7 @@ TarmacParserRecord::TarmacParserRecordEvent::description() const void TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst, - TheISA::PCState pc) + ArmISA::PCState pc) { ostream &outs = Trace::output(); outs << "\nMismatch between gem5 and TARMAC trace @ " << dec << curTick() @@ -776,8 +776,8 @@ TarmacParserRecord::dump() // By default TARMAC splits memory accesses into 4-byte chunks (see // 'loadstore-display-width' option in TARMAC plugin) uint32_t written_data = 0; - unsigned mem_flags = TheISA::TLB::MustBeOne | 3 | - TheISA::TLB::AllowUnaligned; + unsigned mem_flags = ArmISA::TLB::MustBeOne | 3 | + ArmISA::TLB::AllowUnaligned; ISetState isetstate; @@ -1051,7 +1051,7 @@ TarmacParserRecord::readMemNoEffect(Addr addr, uint8_t *data, unsigned size, unsigned flags) { const RequestPtr &req = memReq; - TheISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr()); + ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr()); req->setVirt(0, addr, size, flags, thread->pcState().instAddr(), Request::funcMasterId); |