summaryrefslogtreecommitdiff
path: root/src/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/isa/insts/ldr.isa4
-rw-r--r--src/arch/arm/isa/insts/str.isa4
2 files changed, 6 insertions, 2 deletions
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index cc6b6351b..6919bbca4 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -206,7 +206,9 @@ let {{
# Add memory request flags where necessary
if self.flavor == "exclusive":
self.memFlags.append("Request::LLSC")
- self.memFlags.append("ArmISA::TLB::AlignWord")
+ self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
+ else:
+ self.memFlags.append("ArmISA::TLB::AlignWord")
# Disambiguate the class name for different flavors of loads
if self.flavor != "normal":
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index 589758529..5b0e5b132 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -225,9 +225,11 @@ let {{
self.Name = self.nameFunc(self.post, self.add, self.writeback)
# Add memory request flags where necessary
- self.memFlags.append("ArmISA::TLB::AlignWord")
if self.flavor == "exclusive":
self.memFlags.append("Request::LLSC")
+ self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
+ else:
+ self.memFlags.append("ArmISA::TLB::AlignWord")
# Disambiguate the class name for different flavors of stores
if self.flavor != "normal":