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-rw-r--r--src/arch/arm/kvm/armv8_cpu.cc14
-rw-r--r--src/arch/arm/kvm/armv8_cpu.hh14
2 files changed, 22 insertions, 6 deletions
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 352fb2c80..db2b9c07a 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -114,6 +114,12 @@ const std::vector<ArmV8KvmCPU::MiscRegInfo> ArmV8KvmCPU::miscRegMap = {
MiscRegInfo(INT_REG(fp_regs.fpcr), MISCREG_FPCR, "FPCR"),
};
+const std::set<MiscRegIndex> ArmV8KvmCPU::deviceRegSet = {
+ MISCREG_CNTV_CTL_EL0,
+ MISCREG_CNTV_CVAL_EL0,
+ MISCREG_CNTKCTL_EL1,
+};
+
const std::vector<ArmV8KvmCPU::MiscRegInfo> ArmV8KvmCPU::miscRegIdMap = {
MiscRegInfo(SYS_MPIDR_EL1, MISCREG_MPIDR_EL1, "MPIDR(EL1)"),
};
@@ -317,7 +323,10 @@ ArmV8KvmCPU::updateThreadContext()
for (const auto &ri : getSysRegMap()) {
const auto value(getOneRegU64(ri.kvm));
DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
- tc->setMiscRegNoEffect(ri.idx, value);
+ if (ri.is_device)
+ tc->setMiscReg(ri.idx, value);
+ else
+ tc->setMiscRegNoEffect(ri.idx, value);
}
PCState pc(getOneRegU64(INT_REG(regs.pc)));
@@ -366,7 +375,8 @@ ArmV8KvmCPU::getSysRegMap() const
// Only add implemented registers that we are going to be able
// to write.
if (implemented && writeable)
- sysRegMap.emplace_back(reg, idx, miscRegName[idx]);
+ sysRegMap.emplace_back(reg, idx, miscRegName[idx],
+ deviceRegSet.find(idx) != deviceRegSet.end());
}
return sysRegMap;
diff --git a/src/arch/arm/kvm/armv8_cpu.hh b/src/arch/arm/kvm/armv8_cpu.hh
index 63e03908f..101ccc211 100644
--- a/src/arch/arm/kvm/armv8_cpu.hh
+++ b/src/arch/arm/kvm/armv8_cpu.hh
@@ -40,6 +40,7 @@
#ifndef __ARCH_ARM_KVM_ARMV8_CPU_HH__
#define __ARCH_ARM_KVM_ARMV8_CPU_HH__
+#include <set>
#include <vector>
#include "arch/arm/intregs.hh"
@@ -107,8 +108,9 @@ class ArmV8KvmCPU : public BaseArmKvmCPU
/** Mapping between misc registers in gem5 and registers in KVM */
struct MiscRegInfo {
- MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name)
- : kvm(_kvm), idx(_idx), name(_name) {}
+ MiscRegInfo(uint64_t _kvm, MiscRegIndex _idx, const char *_name,
+ bool _is_device = false)
+ : kvm(_kvm), idx(_idx), name(_name), is_device(_is_device) {}
/** Register index in KVM */
uint64_t kvm;
@@ -116,6 +118,8 @@ class ArmV8KvmCPU : public BaseArmKvmCPU
MiscRegIndex idx;
/** Name to use in debug dumps */
const char *name;
+ /** is device register? (needs 'effectful' state update) */
+ bool is_device;
};
/**
@@ -132,9 +136,11 @@ class ArmV8KvmCPU : public BaseArmKvmCPU
/** Mapping between gem5 integer registers and integer registers in kvm */
static const std::vector<ArmV8KvmCPU::IntRegInfo> intRegMap;
- /** Mapping between gem5 misc registers registers and registers in kvm */
+ /** Mapping between gem5 misc registers and registers in kvm */
static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegMap;
- /** Mapping between gem5 ID misc registers registers and registers in kvm */
+ /** Device registers (needing "effectful" MiscReg writes) */
+ static const std::set<MiscRegIndex> deviceRegSet;
+ /** Mapping between gem5 ID misc registers and registers in kvm */
static const std::vector<ArmV8KvmCPU::MiscRegInfo> miscRegIdMap;
/** Cached mapping between system registers in kvm and misc regs in gem5 */