diff options
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/pseudo_inst.hh | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/src/arch/arm/pseudo_inst.hh b/src/arch/arm/pseudo_inst.hh new file mode 100644 index 000000000..8da25ef87 --- /dev/null +++ b/src/arch/arm/pseudo_inst.hh @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2014 Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Alexandru Dutu + */ + +#ifndef __ARCH_ARM_PSEUDO_INST_HH__ +#define __ARCH_ARM_PSEUDO_INST_HH__ + +#include "arch/generic/pseudo_inst.hh" +#include "base/misc.hh" + +class ThreadContext; + +namespace ArmISA { + using GenericISA::m5Syscall; + using GenericISA::m5PageFault; +} + +#endif // __ARCH_ARM_PSEUDO_INST_HH__ + |