7 files changed, 11 insertions, 11 deletions
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index b4e8536a0..70be40313 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -40,8 +40,8 @@ from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
-from ArmPMU import ArmPMU
-from ISACommon import VecRegRenameMode
+from m5.objects.ArmPMU import ArmPMU
+from m5.objects.ISACommon import VecRegRenameMode
 
 # Enum for DecoderFlavour
 class DecoderFlavour(Enum): vals = ['Generic']
diff --git a/src/arch/arm/ArmNativeTrace.py b/src/arch/arm/ArmNativeTrace.py
index 3101c33de..53ee04a8b 100644
--- a/src/arch/arm/ArmNativeTrace.py
+++ b/src/arch/arm/ArmNativeTrace.py
@@ -28,7 +28,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from CPUTracers import NativeTrace
+from m5.objects.CPUTracers import NativeTrace
 
 class ArmNativeTrace(NativeTrace):
     type = 'ArmNativeTrace'
diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index cb37ff88c..be9dbb86e 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -42,7 +42,7 @@ from m5.SimObject import *
 from m5.params import *
 from m5.params import isNullPointer
 from m5.proxy import *
-from Gic import ArmInterruptPin
+from m5.objects.Gic import ArmInterruptPin
 
 class ProbeEvent(object):
     def __init__(self, pmu, _eventId, obj, *listOfNames):
diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
index 784649914..a804aa8ab 100644
--- a/src/arch/arm/ArmSemihosting.py
+++ b/src/arch/arm/ArmSemihosting.py
@@ -38,8 +38,8 @@
 from m5.params import *
 from m5.SimObject import *
 
-from Serial import SerialDevice
-from Terminal import Terminal
+from m5.objects.Serial import SerialDevice
+from m5.objects.Terminal import Terminal
 
 class ArmSemihosting(SimObject):
     type = 'ArmSemihosting'
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 98ff95918..7ade1e695 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -41,8 +41,8 @@ from m5.options import *
 from m5.SimObject import *
 from m5.util.fdthelper import *
 
-from System import System
-from ArmSemihosting import ArmSemihosting
+from m5.objects.System import System
+from m5.objects.ArmSemihosting import ArmSemihosting
 
 class ArmMachineType(Enum):
     map = {
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 4cac944f1..c5a8122dd 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -40,8 +40,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from BaseTLB import BaseTLB
+from m5.objects.MemObject import MemObject
+from m5.objects.BaseTLB import BaseTLB
 
 # Basic stage 1 translation objects
 class ArmTableWalker(MemObject):
diff --git a/src/arch/arm/tracers/TarmacTrace.py b/src/arch/arm/tracers/TarmacTrace.py
index 8955fadd6..7c0e60f59 100644
--- a/src/arch/arm/tracers/TarmacTrace.py
+++ b/src/arch/arm/tracers/TarmacTrace.py
@@ -38,7 +38,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from InstTracer import InstTracer
+from m5.objects.InstTracer import InstTracer
 
 class TarmacParser(InstTracer):
     type = 'TarmacParser'