3 files changed, 12 insertions, 11 deletions

diff --git a/src/arch/arm/mmapped_ipr.hh b/src/arch/arm/mmapped_ipr.hh
index 0f90ac35d..474aacbcf 100644
--- a/src/arch/arm/mmapped_ipr.hh
+++ b/src/arch/arm/mmapped_ipr.hh
@@ -46,13 +46,13 @@ class ThreadContext;
 
 namespace ArmISA
 {
-inline Tick
+inline Cycles
 handleIprRead(ThreadContext *xc, Packet *pkt)
 {
     panic("No implementation for handleIprRead in ARM\n");
 }
 
-inline Tick
+inline Cycles
 handleIprWrite(ThreadContext *xc, Packet *pkt)
 {
     panic("No implementation for handleIprWrite in ARM\n");
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index ffa193fbe..77cc662b3 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -240,15 +240,16 @@ TableWalker::processWalk()
     if (currState->timing) {
         port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
                        &doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
-                       currState->tc->getCpuPtr()->ticks(1), flag);
-        DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
+                       currState->tc->getCpuPtr()->clockPeriod(), flag);
+        DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before "
+                "adding: %d\n",
                 stateQueueL1.size());
         stateQueueL1.push_back(currState);
         currState = NULL;
     } else if (!currState->functional) {
         port.dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
                        NULL, (uint8_t*)&currState->l1Desc.data,
-                       currState->tc->getCpuPtr()->ticks(1), flag);
+                       currState->tc->getCpuPtr()->clockPeriod(), flag);
         doL1Descriptor();
         f = currState->fault;
     } else {
@@ -588,12 +589,12 @@ TableWalker::doL1Descriptor()
         if (currState->timing) {
             currState->delayed = true;
             port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
-                    &doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
-                    currState->tc->getCpuPtr()->ticks(1));
+                           &doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
+                           currState->tc->getCpuPtr()->clockPeriod());
         } else if (!currState->functional) {
             port.dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
-                    NULL, (uint8_t*)&currState->l2Desc.data,
-                    currState->tc->getCpuPtr()->ticks(1));
+                           NULL, (uint8_t*)&currState->l2Desc.data,
+                           currState->tc->getCpuPtr()->clockPeriod());
             doL2Descriptor();
         } else {
             RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0,
@@ -758,7 +759,7 @@ void
 TableWalker::nextWalk(ThreadContext *tc)
 {
     if (pendingQueue.size())
-        schedule(doProcessEvent, tc->getCpuPtr()->clockEdge(1));
+        schedule(doProcessEvent, tc->getCpuPtr()->clockEdge(Cycles(1)));
 }
 
 
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index b3b400e3c..e4fc658e0 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -102,7 +102,7 @@ void zeroRegisters(TC *tc);
 
 inline void startupCPU(ThreadContext *tc, int cpuId)
 {
-    tc->activate(0);
+    tc->activate(Cycles(0));
 }
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);