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-rw-r--r--src/arch/arm/isa/templates/basic.isa2
-rw-r--r--src/arch/arm/isa/templates/branch.isa12
-rw-r--r--src/arch/arm/isa/templates/branch64.isa10
-rw-r--r--src/arch/arm/isa/templates/data64.isa20
-rw-r--r--src/arch/arm/isa/templates/mem.isa24
-rw-r--r--src/arch/arm/isa/templates/mem64.isa2
-rw-r--r--src/arch/arm/isa/templates/misc.isa36
-rw-r--r--src/arch/arm/isa/templates/misc64.isa4
-rw-r--r--src/arch/arm/isa/templates/mult.isa4
-rw-r--r--src/arch/arm/isa/templates/pred.isa6
-rw-r--r--src/arch/arm/isa/templates/vfp.isa8
-rw-r--r--src/arch/arm/isa/templates/vfp64.isa10
12 files changed, 69 insertions, 69 deletions
diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa
index de4506e05..e202a4768 100644
--- a/src/arch/arm/isa/templates/basic.isa
+++ b/src/arch/arm/isa/templates/basic.isa
@@ -73,7 +73,7 @@ def template BasicConstructor {{
}};
def template BasicConstructor64 {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+ %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
}
diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index ee06bf573..c8efdb7a6 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -48,7 +48,7 @@ class %(class_name)s : public %(base_class)s
}};
def template BranchImmConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
int32_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
{
@@ -81,7 +81,7 @@ class %(class_name)s : public %(base_class)s
}};
def template BranchImmCondConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
int32_t _imm,
ConditionCode _condCode)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -110,7 +110,7 @@ class %(class_name)s : public %(base_class)s
}};
def template BranchRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _op1)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
{
@@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s
}};
def template BranchRegCondConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _op1,
ConditionCode _condCode)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -187,7 +187,7 @@ class %(class_name)s : public %(base_class)s
}};
def template BranchRegRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _op1,
IntRegIndex _op2)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
@@ -218,7 +218,7 @@ class %(class_name)s : public %(base_class)s
// Only used by CBNZ, CBZ which is conditional based on
// a register value even though the instruction is always unconditional.
def template BranchImmRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
int32_t _imm,
IntRegIndex _op1)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
diff --git a/src/arch/arm/isa/templates/branch64.isa b/src/arch/arm/isa/templates/branch64.isa
index 84b3e6ae7..241d12260 100644
--- a/src/arch/arm/isa/templates/branch64.isa
+++ b/src/arch/arm/isa/templates/branch64.isa
@@ -48,7 +48,7 @@ class %(class_name)s : public %(base_class)s
}};
def template BranchImm64Constructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
int64_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
{
@@ -68,7 +68,7 @@ class %(class_name)s : public %(base_class)s
}};
def template BranchImmCond64Constructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
int64_t _imm,
ConditionCode _condCode)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -89,7 +89,7 @@ class %(class_name)s : public %(base_class)s
}};
def template BranchReg64Constructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _op1)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
{
@@ -109,7 +109,7 @@ class %(class_name)s : public %(base_class)s
}};
def template BranchImmReg64Constructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
int64_t _imm,
IntRegIndex _op1)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
@@ -130,7 +130,7 @@ class %(class_name)s : public %(base_class)s
}};
def template BranchImmImmReg64Constructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
int64_t _imm1, int64_t _imm2,
IntRegIndex _op1)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
diff --git a/src/arch/arm/isa/templates/data64.isa b/src/arch/arm/isa/templates/data64.isa
index b6f7ce8d0..7b0438a01 100644
--- a/src/arch/arm/isa/templates/data64.isa
+++ b/src/arch/arm/isa/templates/data64.isa
@@ -49,7 +49,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataXImmConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
uint64_t _imm)
@@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataXSRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
@@ -99,7 +99,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataXERegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
@@ -124,7 +124,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataX1RegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
@@ -145,7 +145,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataX2RegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2)
@@ -168,7 +168,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataX2RegImmConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
@@ -192,7 +192,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataX3RegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
@@ -216,7 +216,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataXCondCompImmConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _op1,
uint64_t _imm,
ConditionCode _condCode,
@@ -241,7 +241,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataXCondCompRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _op1,
IntRegIndex _op2,
ConditionCode _condCode,
@@ -266,7 +266,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataXCondSelConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 7682c277d..e052cbb9d 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -860,7 +860,7 @@ def template CompleteAccDeclare {{
}};
def template RfeConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _base, int _mode, bool _wb)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_base, (AddrMode)_mode, _wb)
@@ -889,7 +889,7 @@ def template RfeConstructor {{
}};
def template SrsConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _regMode, int _mode, bool _wb)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(OperatingMode)_regMode, (AddrMode)_mode, _wb)
@@ -912,7 +912,7 @@ def template SrsConstructor {{
}};
def template SwapConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _op1, uint32_t _base)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
@@ -927,7 +927,7 @@ def template SwapConstructor {{
}};
def template LoadStoreDImmConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _dest2,
uint32_t _base, bool _add, int32_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -952,7 +952,7 @@ def template LoadStoreDImmConstructor {{
}};
def template StoreExDImmConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _result, uint32_t _dest, uint32_t _dest2,
uint32_t _base, bool _add, int32_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -979,7 +979,7 @@ def template StoreExDImmConstructor {{
}};
def template LoadStoreImmConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
@@ -1002,7 +1002,7 @@ def template LoadStoreImmConstructor {{
}};
def template StoreExImmConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _result, uint32_t _dest, uint32_t _base,
bool _add, int32_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -1028,7 +1028,7 @@ def template StoreExImmConstructor {{
}};
def template StoreDRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -1056,7 +1056,7 @@ def template StoreDRegConstructor {{
}};
def template StoreRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add,
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -1083,7 +1083,7 @@ def template StoreRegConstructor {{
}};
def template LoadDRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -1123,7 +1123,7 @@ def template LoadDRegConstructor {{
}};
def template LoadRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add,
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -1189,7 +1189,7 @@ def template LoadRegConstructor {{
}};
def template LoadImmConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
(IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa
index 87dcba988..4d4b27ba9 100644
--- a/src/arch/arm/isa/templates/mem64.isa
+++ b/src/arch/arm/isa/templates/mem64.isa
@@ -589,7 +589,7 @@ def template LoadStoreImmDU64Constructor {{
}};
def template StoreImmDEx64Constructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
IntRegIndex _base, int64_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 36db5b6c2..c3866a51f 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -49,7 +49,7 @@ class %(class_name)s : public %(base_class)s
}};
def template MrsConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
{
@@ -78,7 +78,7 @@ class %(class_name)s : public %(base_class)s
}};
def template MrsBankedRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
uint8_t _sysM,
bool _r)
@@ -109,7 +109,7 @@ class %(class_name)s : public %(base_class)s
}};
def template MsrBankedRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _op1,
uint8_t _sysM,
bool _r)
@@ -137,7 +137,7 @@ class %(class_name)s : public %(base_class)s
}};
def template MsrRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _op1,
uint8_t mask)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
@@ -163,7 +163,7 @@ class %(class_name)s : public %(base_class)s
}};
def template MsrImmConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t imm,
uint8_t mask)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask)
@@ -190,7 +190,7 @@ class %(class_name)s : public %(base_class)s
}};
def template MrrcOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex op1,
IntRegIndex dest,
IntRegIndex dest2,
@@ -220,7 +220,7 @@ class %(class_name)s : public %(base_class)s
}};
def template McrrOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex op1,
IntRegIndex op2,
IntRegIndex dest,
@@ -249,7 +249,7 @@ class %(class_name)s : public %(base_class)s
}};
def template ImmOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
{
%(constructor)s;
@@ -273,7 +273,7 @@ class %(class_name)s : public %(base_class)s
}};
def template RegImmOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, uint64_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
{
@@ -299,7 +299,7 @@ class %(class_name)s : public %(base_class)s
}};
def template RegRegOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
{
@@ -326,7 +326,7 @@ class %(class_name)s : public %(base_class)s
}};
def template RegRegRegImmOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
@@ -357,7 +357,7 @@ class %(class_name)s : public %(base_class)s
}};
def template RegRegRegRegOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
@@ -387,7 +387,7 @@ class %(class_name)s : public %(base_class)s
}};
def template RegRegRegOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2)
@@ -417,7 +417,7 @@ class %(class_name)s : public %(base_class)s
}};
def template RegRegImmOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
uint64_t _imm)
@@ -446,7 +446,7 @@ class %(class_name)s : public %(base_class)s
}};
def template RegImmImmOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
uint64_t _imm1,
uint64_t _imm2)
@@ -476,7 +476,7 @@ class %(class_name)s : public %(base_class)s
}};
def template RegRegImmImmOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
uint64_t _imm1,
@@ -506,7 +506,7 @@ class %(class_name)s : public %(base_class)s
}};
def template RegImmRegOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
uint64_t _imm,
IntRegIndex _op1)
@@ -536,7 +536,7 @@ class %(class_name)s : public %(base_class)s
}};
def template RegImmRegShiftOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
uint64_t _imm,
IntRegIndex _op1,
diff --git a/src/arch/arm/isa/templates/misc64.isa b/src/arch/arm/isa/templates/misc64.isa
index 09d3d4470..3ccb3dc17 100644
--- a/src/arch/arm/isa/templates/misc64.isa
+++ b/src/arch/arm/isa/templates/misc64.isa
@@ -51,7 +51,7 @@ class %(class_name)s : public %(base_class)s
}};
def template RegRegImmImmOp64Constructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
uint64_t _imm1,
@@ -77,7 +77,7 @@ class %(class_name)s : public %(base_class)s
}};
def template RegRegRegImmOp64Constructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
diff --git a/src/arch/arm/isa/templates/mult.isa b/src/arch/arm/isa/templates/mult.isa
index dd4847fd4..0099e5c9d 100644
--- a/src/arch/arm/isa/templates/mult.isa
+++ b/src/arch/arm/isa/templates/mult.isa
@@ -49,7 +49,7 @@ class %(class_name)s : public %(base_class)s
}};
def template Mult3Constructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _reg0,
IntRegIndex _reg1,
IntRegIndex _reg2)
@@ -78,7 +78,7 @@ class %(class_name)s : public %(base_class)s
}};
def template Mult4Constructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _reg0,
IntRegIndex _reg1,
IntRegIndex _reg2,
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 42f515a3c..9973e9a2a 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -62,7 +62,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataImmConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
uint32_t _imm,
@@ -101,7 +101,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
@@ -146,7 +146,7 @@ class %(class_name)s : public %(base_class)s
}};
def template DataRegRegConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa
index 176b6604c..fbd7275d5 100644
--- a/src/arch/arm/isa/templates/vfp.isa
+++ b/src/arch/arm/isa/templates/vfp.isa
@@ -166,7 +166,7 @@ class %(class_name)s : public %(base_class)s
}};
def template FpRegRegOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1,
VfpMicroMode mode)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -193,7 +193,7 @@ class %(class_name)s : public %(base_class)s
}};
def template FpRegImmOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, mode)
@@ -220,7 +220,7 @@ class %(class_name)s : public %(base_class)s
}};
def template FpRegRegImmOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
uint64_t _imm,
@@ -250,7 +250,7 @@ class %(class_name)s : public %(base_class)s
}};
def template FpRegRegRegOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
diff --git a/src/arch/arm/isa/templates/vfp64.isa b/src/arch/arm/isa/templates/vfp64.isa
index 0935cd78a..761a853a9 100644
--- a/src/arch/arm/isa/templates/vfp64.isa
+++ b/src/arch/arm/isa/templates/vfp64.isa
@@ -38,7 +38,7 @@
// Authors: Thomas Grocutt
def template AA64FpRegRegOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, IntRegIndex _op1,
VfpMicroMode mode)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -52,7 +52,7 @@ def template AA64FpRegRegOpConstructor {{
}};
def template AA64FpRegImmOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, mode)
@@ -65,7 +65,7 @@ def template AA64FpRegImmOpConstructor {{
}};
def template AA64FpRegRegImmOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
uint64_t _imm,
@@ -81,7 +81,7 @@ def template AA64FpRegRegImmOpConstructor {{
}};
def template AA64FpRegRegRegOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
@@ -109,7 +109,7 @@ class %(class_name)s : public %(base_class)s
}};
def template AA64FpRegRegRegRegOpConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex _dest,
IntRegIndex _op1,
IntRegIndex _op2,
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 08:27:16 +0000