diff options
Diffstat (limited to 'src/arch/arm')
-rwxr-xr-x | src/arch/arm/stage2_mmu.cc | 6 | ||||
-rwxr-xr-x | src/arch/arm/stage2_mmu.hh | 2 |
2 files changed, 0 insertions, 8 deletions
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc index 3525768e0..a2ae8cc73 100755 --- a/src/arch/arm/stage2_mmu.cc +++ b/src/arch/arm/stage2_mmu.cc @@ -141,12 +141,6 @@ Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req, } } -unsigned int -Stage2MMU::drain(DrainManager *dm) -{ - return port.drain(dm); -} - ArmISA::Stage2MMU * ArmStage2MMUParams::create() { diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh index b42f213e8..9543c7471 100755 --- a/src/arch/arm/stage2_mmu.hh +++ b/src/arch/arm/stage2_mmu.hh @@ -112,8 +112,6 @@ class Stage2MMU : public SimObject */ DmaPort& getPort() { return port; } - unsigned int drain(DrainManager *dm); - Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr, uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional); Fault readDataTimed(ThreadContext *tc, Addr descAddr, |