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-rw-r--r--src/arch/arm/miscregs.cc23
-rw-r--r--src/arch/arm/miscregs.hh2
2 files changed, 25 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index a8abbf692..3a64b557a 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -63,9 +63,32 @@ decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
return NUM_MISCREGS;
}
default:
+ warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+ crn, opc1, crm, opc2);
+ return NUM_MISCREGS;
+ }
+ case 1:
+ switch (opc1) {
+ case 6:
+ switch (crm) {
+ case 0:
+ switch (opc2) {
+ case 0:
+ return MISCREG_TEEHBR;
+ default:
+ warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+ crn, opc1, crm, opc2);
+ return NUM_MISCREGS;
+ }
+ default:
warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
crn, opc1, crm, opc2);
return NUM_MISCREGS;
+ }
+ default:
+ warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+ crn, opc1, crm, opc2);
+ return NUM_MISCREGS;
}
default:
warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 02c03a7fc..13234ddf5 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -121,6 +121,7 @@ namespace ArmISA
MISCREG_DBGDEVID2,
MISCREG_DBGDEVID1,
MISCREG_DBGDEVID,
+ MISCREG_TEEHBR,
// CP15 registers
MISCREG_CP15_START,
@@ -288,6 +289,7 @@ namespace ArmISA
"DBGDEVID2",
"DBGDEVID1",
"DBGDEVID",
+ "TEEHBR",
"sctlr", "dccisw", "dccimvac", "dccmvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"cp15isb", "cp15dsb", "cp15dmb", "cpacr",