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-rw-r--r--src/arch/arm/ArmISA.py5
-rw-r--r--src/arch/arm/insts/static_inst.cc6
-rw-r--r--src/arch/arm/insts/static_inst.hh1
-rw-r--r--src/arch/arm/isa.cc1
-rw-r--r--src/arch/arm/isa.hh40
-rw-r--r--src/arch/arm/nativetrace.cc10
-rw-r--r--src/arch/arm/registers.hh18
-rw-r--r--src/arch/arm/remote_gdb.cc10
-rw-r--r--src/arch/arm/remote_gdb.hh4
-rw-r--r--src/arch/arm/utility.cc3
10 files changed, 88 insertions, 10 deletions
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 73ef4a09d..7956570bd 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -41,6 +41,7 @@ from m5.proxy import *
from m5.SimObject import SimObject
from ArmPMU import ArmPMU
+from ISACommon import VecRegRenameMode
# Enum for DecoderFlavour
class DecoderFlavour(Enum): vals = ['Generic']
@@ -86,6 +87,10 @@ class ArmISA(SimObject):
id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
"AArch64 Auxiliary Feature Register 1")
+ # Initial vector register rename mode
+ vecRegRenameMode = Param.VecRegRenameMode('Full',
+ "Initial rename mode for vecregs")
+
# 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
"AArch64 Debug Feature Register 0")
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 99d1b817d..8501715d5 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -331,6 +331,12 @@ ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const
}
void
+ArmStaticInst::printVecReg(std::ostream &os, RegIndex reg_idx) const
+{
+ ccprintf(os, "v%d", reg_idx);
+}
+
+void
ArmStaticInst::printCCReg(std::ostream &os, RegIndex reg_idx) const
{
ccprintf(os, "cc_%s", ArmISA::ccRegName[reg_idx]);
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 19af99a0f..486d30fe4 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -157,6 +157,7 @@ class ArmStaticInst : public StaticInst
/// dependence tag number (FP or int).
void printIntReg(std::ostream &os, RegIndex reg_idx) const;
void printFloatReg(std::ostream &os, RegIndex reg_idx) const;
+ void printVecReg(std::ostream &os, RegIndex reg_idx) const;
void printCCReg(std::ostream &os, RegIndex reg_idx) const;
void printMiscReg(std::ostream &os, RegIndex reg_idx) const;
void printMnemonic(std::ostream &os,
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index c54d7746d..a490e5fb7 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -209,6 +209,7 @@ ISA::ISA(Params *p)
: SimObject(p),
system(NULL),
_decoderFlavour(p->decoderFlavour),
+ _vecRegRenameMode(p->vecRegRenameMode),
pmu(p->pmu),
lookUpMiscReg(NUM_MISCREGS, {0,0})
{
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 8de90dc93..e96de7922 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -48,7 +48,9 @@
#include "arch/arm/system.hh"
#include "arch/arm/tlb.hh"
#include "arch/arm/types.hh"
+#include "arch/generic/traits.hh"
#include "debug/Checkpoint.hh"
+#include "enums/VecRegRenameMode.hh"
#include "sim/sim_object.hh"
#include "enums/DecoderFlavour.hh"
@@ -68,6 +70,7 @@ namespace ArmISA
// Micro Architecture
const Enums::DecoderFlavour _decoderFlavour;
+ const Enums::VecRegRenameMode _vecRegRenameMode;
/** Dummy device for to handle non-existing ISA devices */
DummyISADevice dummyDevice;
@@ -185,6 +188,10 @@ namespace ArmISA
return RegId(IntRegClass, flattenIntIndex(regId.index()));
case FloatRegClass:
return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+ case VecRegClass:
+ return RegId(VecRegClass, flattenVecIndex(regId.index()));
+ case VecElemClass:
+ return RegId(VecElemClass, flattenVecElemIndex(regId.index()));
case CCRegClass:
return RegId(CCRegClass, flattenCCIndex(regId.index()));
case MiscRegClass:
@@ -233,6 +240,20 @@ namespace ArmISA
}
int
+ flattenVecIndex(int reg) const
+ {
+ assert(reg >= 0);
+ return reg;
+ }
+
+ int
+ flattenVecElemIndex(int reg) const
+ {
+ assert(reg >= 0);
+ return reg;
+ }
+
+ int
flattenCCIndex(int reg) const
{
assert(reg >= 0);
@@ -406,6 +427,12 @@ namespace ArmISA
Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; }
+ Enums::VecRegRenameMode
+ vecRegRenameMode() const
+ {
+ return _vecRegRenameMode;
+ }
+
/// Explicitly import the otherwise hidden startup
using SimObject::startup;
@@ -417,4 +444,17 @@ namespace ArmISA
};
}
+template<>
+struct initRenameMode<ArmISA::ISA>
+{
+ static Enums::VecRegRenameMode mode(const ArmISA::ISA* isa)
+ {
+ return isa->vecRegRenameMode();
+ }
+ static bool equals(const ArmISA::ISA* isa1, const ArmISA::ISA* isa2)
+ {
+ return mode(isa1) == mode(isa2);
+ }
+};
+
#endif
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index fcb13fb2a..395232e00 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2011, 2014 ARM Limited
+ * Copyright (c) 2010-2011, 2014, 2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -125,10 +125,10 @@ Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
newState[STATE_CPSR] = cpsr;
changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
- for (int i = 0; i < NumFloatV7ArchRegs; i += 2) {
- newState[STATE_F0 + (i >> 1)] =
- static_cast<uint64_t>(tc->readFloatRegBits(i + 1)) << 32 |
- tc->readFloatRegBits(i);
+ for (int i = 0; i < NumVecV7ArchRegs; i++) {
+ auto vec(tc->readVecReg(RegId(VecRegClass,i)).as<uint64_t, 2>());
+ newState[STATE_F0 + 2*i] = vec[0];
+ newState[STATE_F0 + 2*i + 1] = vec[1];
}
newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) |
tc->readCCReg(CCREG_FP);
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 2e1ad1881..0a617e4dc 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2011, 2014 ARM Limited
+ * Copyright (c) 2010-2011, 2014, 2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -43,10 +43,11 @@
#ifndef __ARCH_ARM_REGISTERS_HH__
#define __ARCH_ARM_REGISTERS_HH__
+#include "arch/arm/ccregs.hh"
#include "arch/arm/generated/max_inst_regs.hh"
#include "arch/arm/intregs.hh"
-#include "arch/arm/ccregs.hh"
#include "arch/arm/miscregs.hh"
+#include "arch/generic/vec_reg.hh"
namespace ArmISA {
@@ -64,6 +65,13 @@ typedef uint64_t IntReg;
typedef uint32_t FloatRegBits;
typedef float FloatReg;
+// Number of VecElem per Vector Register, computed based on the vector length
+constexpr unsigned NumVecElemPerVecReg = 4;
+using VecElem = uint32_t;
+using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
+using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
+using VecRegContainer = VecReg::Container;
+
// cop-0/cop-1 system control register
typedef uint64_t MiscReg;
@@ -76,15 +84,19 @@ const int NumIntArchRegs = NUM_ARCH_INTREGS;
const int NumFloatV7ArchRegs = 64;
const int NumFloatV8ArchRegs = 128;
const int NumFloatSpecialRegs = 32;
+const int NumVecV7ArchRegs = 64;
+const int NumVecV8ArchRegs = 32;
+const int NumVecSpecialRegs = 8;
const int NumIntRegs = NUM_INTREGS;
const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
+const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs;
const int NumCCRegs = NUM_CCREGS;
const int NumMiscRegs = NUM_MISCREGS;
#define ISA_HAS_CC_REGS
-const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
+const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + NumMiscRegs;
// semantically meaningful register indices
const int ReturnValueReg = 0;
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index eefe62b42..d934d53d3 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -1,7 +1,7 @@
/*
* Copyright 2015 LabWare
* Copyright 2014 Google Inc.
- * Copyright (c) 2010, 2013 ARM Limited
+ * Copyright (c) 2010, 2013, 2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -212,6 +212,10 @@ RemoteGDB::AArch64GdbRegCache::getRegs(ThreadContext *context)
r.v[i + 2] = context->readFloatRegBits(i + 0);
r.v[i + 3] = context->readFloatRegBits(i + 1);
}
+
+ for (int i = 0; i < 32; i ++) {
+ r.vec[i] = context->readVecReg(RegId(VecRegClass,i));
+ }
}
void
@@ -234,6 +238,10 @@ RemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context) const
context->setFloatRegBits(i + 0, r.v[i + 2]);
context->setFloatRegBits(i + 1, r.v[i + 3]);
}
+
+ for (int i = 0; i < 32; i ++) {
+ context->setVecReg(RegId(VecRegClass, i), r.vec[i]);
+ }
}
void
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index acd6f32d2..328fbadb3 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -1,7 +1,7 @@
/*
* Copyright 2015 LabWare
* Copyright 2014 Google, Inc.
- * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2013, 2016 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -51,6 +51,7 @@
#include <algorithm>
#include "arch/arm/utility.hh"
+#include "arch/generic/vec_reg.hh"
#include "base/remote_gdb.hh"
class System;
@@ -96,6 +97,7 @@ class RemoteGDB : public BaseRemoteGDB
uint64_t pc;
uint64_t cpsr;
uint32_t v[32*4];
+ ArmISA::VecRegContainer vec[32];
} r;
public:
char *data() const { return (char *)&r; }
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 1437801a2..a58ca8111 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -154,6 +154,9 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
for (int i = 0; i < NumFloatRegs; i++)
dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
+ for (int i = 0; i < NumVecRegs; i++)
+ dest->setVecRegFlat(i, src->readVecRegFlat(i));
+
for (int i = 0; i < NumCCRegs; i++)
dest->setCCReg(i, src->readCCReg(i));
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 06:07:53 +0000