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-rw-r--r--src/arch/arm/insts/static_inst.hh1
-rw-r--r--src/arch/arm/insts/vfp.hh3
-rw-r--r--src/arch/arm/isa/templates/basic.isa2
-rw-r--r--src/arch/arm/miscregs.cc2
4 files changed, 6 insertions, 2 deletions
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index fa850190f..5af97b796 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -46,6 +46,7 @@
#include "arch/arm/utility.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "sim/byteswap.hh"
namespace ArmISA
{
diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh
index 57b74d040..b3582a351 100644
--- a/src/arch/arm/insts/vfp.hh
+++ b/src/arch/arm/insts/vfp.hh
@@ -107,6 +107,9 @@ enum VfpRoundingMode
VfpRoundZero = 3
};
+static inline float bitsToFp(uint64_t, float);
+static inline uint32_t fpToBits(float);
+
template <class fpType>
static inline bool
flushToZero(fpType &op)
diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa
index 0728b66e3..b3878b89a 100644
--- a/src/arch/arm/isa/templates/basic.isa
+++ b/src/arch/arm/isa/templates/basic.isa
@@ -49,7 +49,7 @@ def template BasicDeclare {{
// Basic instruction class constructor template.
def template BasicConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+ %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index db097c653..c31818377 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -411,7 +411,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
}
break;
case 11:
- if (opc1 >= 0 && opc1 <=7) {
+ if (opc1 <=7) {
switch (crm) {
case 0:
case 1: