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-rw-r--r--src/arch/arm/miscregs.cc10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index e1ddbf9d3..08e37bb70 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -2082,9 +2082,12 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
}
break;
}
- break;
+ M5_FALLTHROUGH;
+ default:
+ // S3_<op1>_11_<Cm>_<op2>
+ return MISCREG_IMPDEF_UNIMPL;
}
- break;
+ M5_UNREACHABLE;
case 12:
switch (op1) {
case 0:
@@ -2370,7 +2373,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
}
break;
}
- break;
+ // S3_<op1>_15_<Cm>_<op2>
+ return MISCREG_IMPDEF_UNIMPL;
}
break;
}