diff options
Diffstat (limited to 'src/arch/arm')
27 files changed, 444 insertions, 307 deletions
diff --git a/src/arch/arm/insts/branch64.hh b/src/arch/arm/insts/branch64.hh index 48881e0c2..731c1869c 100644 --- a/src/arch/arm/insts/branch64.hh +++ b/src/arch/arm/insts/branch64.hh @@ -55,12 +55,14 @@ class BranchImm64 : public ArmStaticInst ArmStaticInst(mnem, _machInst, __opClass), imm(_imm) {} - ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; + ArmISA::PCState branchTarget( + const ArmISA::PCState &branchPC) const override; /// Explicitly import the otherwise hidden branchTarget using StaticInst::branchTarget; - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // Conditionally Branch to a target computed with an immediate @@ -75,7 +77,8 @@ class BranchImmCond64 : public BranchImm64 BranchImm64(mnem, _machInst, __opClass, _imm), condCode(_condCode) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // Branch to a target computed with a register @@ -90,7 +93,8 @@ class BranchReg64 : public ArmStaticInst ArmStaticInst(mnem, _machInst, __opClass), op1(_op1) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // Ret instruction @@ -102,7 +106,8 @@ class BranchRet64 : public BranchReg64 BranchReg64(mnem, _machInst, __opClass, _op1) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // Eret instruction @@ -113,7 +118,8 @@ class BranchEret64 : public ArmStaticInst ArmStaticInst(mnem, _machInst, __opClass) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // Branch to a target computed with an immediate and a register @@ -129,12 +135,14 @@ class BranchImmReg64 : public ArmStaticInst ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1) {} - ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; + ArmISA::PCState branchTarget( + const ArmISA::PCState &branchPC) const override; /// Explicitly import the otherwise hidden branchTarget using StaticInst::branchTarget; - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // Branch to a target computed with two immediates @@ -153,12 +161,14 @@ class BranchImmImmReg64 : public ArmStaticInst imm1(_imm1), imm2(_imm2), op1(_op1) {} - ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; + ArmISA::PCState branchTarget( + const ArmISA::PCState &branchPC) const override; /// Explicitly import the otherwise hidden branchTarget using StaticInst::branchTarget; - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; } diff --git a/src/arch/arm/insts/data64.hh b/src/arch/arm/insts/data64.hh index 8c0677b3d..d423802b5 100644 --- a/src/arch/arm/insts/data64.hh +++ b/src/arch/arm/insts/data64.hh @@ -57,7 +57,8 @@ class DataXImmOp : public ArmStaticInst dest(_dest), op1(_op1), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataXImmOnlyOp : public ArmStaticInst @@ -72,7 +73,8 @@ class DataXImmOnlyOp : public ArmStaticInst dest(_dest), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataXSRegOp : public ArmStaticInst @@ -90,7 +92,8 @@ class DataXSRegOp : public ArmStaticInst shiftAmt(_shiftAmt), shiftType(_shiftType) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataXERegOp : public ArmStaticInst @@ -108,7 +111,8 @@ class DataXERegOp : public ArmStaticInst extendType(_extendType), shiftAmt(_shiftAmt) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataX1RegOp : public ArmStaticInst @@ -121,7 +125,8 @@ class DataX1RegOp : public ArmStaticInst ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataX1RegImmOp : public ArmStaticInst @@ -136,7 +141,8 @@ class DataX1RegImmOp : public ArmStaticInst imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataX1Reg2ImmOp : public ArmStaticInst @@ -152,7 +158,8 @@ class DataX1Reg2ImmOp : public ArmStaticInst imm1(_imm1), imm2(_imm2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataX2RegOp : public ArmStaticInst @@ -166,7 +173,8 @@ class DataX2RegOp : public ArmStaticInst dest(_dest), op1(_op1), op2(_op2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataX2RegImmOp : public ArmStaticInst @@ -182,7 +190,8 @@ class DataX2RegImmOp : public ArmStaticInst dest(_dest), op1(_op1), op2(_op2), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataX3RegOp : public ArmStaticInst @@ -197,7 +206,8 @@ class DataX3RegOp : public ArmStaticInst dest(_dest), op1(_op1), op2(_op2), op3(_op3) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataXCondCompImmOp : public ArmStaticInst @@ -215,7 +225,8 @@ class DataXCondCompImmOp : public ArmStaticInst op1(_op1), imm(_imm), condCode(_condCode), defCc(_defCc) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataXCondCompRegOp : public ArmStaticInst @@ -232,7 +243,8 @@ class DataXCondCompRegOp : public ArmStaticInst op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataXCondSelOp : public ArmStaticInst @@ -248,7 +260,8 @@ class DataXCondSelOp : public ArmStaticInst dest(_dest), op1(_op1), op2(_op2), condCode(_condCode) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; } diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh index 412337d06..b974e268e 100644 --- a/src/arch/arm/insts/macromem.hh +++ b/src/arch/arm/insts/macromem.hh @@ -73,7 +73,7 @@ class MicroOp : public PredOp public: void - advancePC(PCState &pcState) const + advancePC(PCState &pcState) const override { if (flags[IsLastMicroop]) { pcState.uEnd(); @@ -94,7 +94,7 @@ class MicroOpX : public ArmStaticInst public: void - advancePC(PCState &pcState) const + advancePC(PCState &pcState) const override { if (flags[IsLastMicroop]) { pcState.uEnd(); @@ -263,7 +263,8 @@ class MicroSetPCCPSR : public MicroOp { } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; /** @@ -281,7 +282,8 @@ class MicroIntMov : public MicroOp { } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; /** @@ -300,7 +302,8 @@ class MicroIntImmOp : public MicroOp { } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MicroIntImmXOp : public MicroOpX @@ -316,7 +319,8 @@ class MicroIntImmXOp : public MicroOpX { } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; /** @@ -334,7 +338,8 @@ class MicroIntOp : public MicroOp { } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MicroIntRegXOp : public MicroOp @@ -353,7 +358,8 @@ class MicroIntRegXOp : public MicroOp { } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; /** @@ -392,7 +398,8 @@ class MicroMemOp : public MicroIntImmOp { } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MicroMemPairOp : public MicroOp @@ -412,7 +419,8 @@ class MicroMemPairOp : public MicroOp { } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; /** diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh index ddd196676..da4dac3f3 100644 --- a/src/arch/arm/insts/mem.hh +++ b/src/arch/arm/insts/mem.hh @@ -60,7 +60,8 @@ class Swap : public PredOp dest(_dest), op1(_op1), base(_base) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MightBeMicro : public PredOp @@ -118,13 +119,14 @@ class RfeOp : public MightBeMicro } StaticInstPtr - fetchMicroop(MicroPC microPC) const + fetchMicroop(MicroPC microPC) const override { assert(uops != NULL && microPC < numMicroops); return uops[microPC]; } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; // The address is a base register plus an immediate. @@ -158,13 +160,14 @@ class SrsOp : public MightBeMicro } StaticInstPtr - fetchMicroop(MicroPC microPC) const + fetchMicroop(MicroPC microPC) const override { assert(uops != NULL && microPC < numMicroops); return uops[microPC]; } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class Memory : public MightBeMicro @@ -198,7 +201,7 @@ class Memory : public MightBeMicro } StaticInstPtr - fetchMicroop(MicroPC microPC) const + fetchMicroop(MicroPC microPC) const override { assert(uops != NULL && microPC < numMicroops); return uops[microPC]; diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh index 7ad2f52eb..4f662831d 100644 --- a/src/arch/arm/insts/mem64.hh +++ b/src/arch/arm/insts/mem64.hh @@ -56,7 +56,8 @@ class SysDC64 : public ArmStaticInst : ArmStaticInst(mnem, _machInst, __opClass), base(_base), dest((IntRegIndex)miscReg), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MightBeMicro64 : public ArmStaticInst @@ -113,7 +114,7 @@ class Memory64 : public MightBeMicro64 } StaticInstPtr - fetchMicroop(MicroPC microPC) const + fetchMicroop(MicroPC microPC) const override { assert(uops != NULL && microPC < numMicroops); return uops[microPC]; @@ -136,7 +137,8 @@ class MemoryImm64 : public Memory64 : Memory64(mnem, _machInst, __opClass, _dest, _base), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MemoryDImm64 : public MemoryImm64 @@ -151,7 +153,8 @@ class MemoryDImm64 : public MemoryImm64 dest2(_dest2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MemoryDImmEx64 : public MemoryDImm64 @@ -166,7 +169,8 @@ class MemoryDImmEx64 : public MemoryDImm64 _base, _imm), result(_result) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MemoryPreIndex64 : public MemoryImm64 @@ -178,7 +182,8 @@ class MemoryPreIndex64 : public MemoryImm64 : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MemoryPostIndex64 : public MemoryImm64 @@ -190,7 +195,8 @@ class MemoryPostIndex64 : public MemoryImm64 : MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MemoryReg64 : public Memory64 @@ -208,7 +214,8 @@ class MemoryReg64 : public Memory64 offset(_offset), type(_type), shiftAmt(_shiftAmt) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MemoryRaw64 : public Memory64 @@ -219,7 +226,8 @@ class MemoryRaw64 : public Memory64 : Memory64(mnem, _machInst, __opClass, _dest, _base) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MemoryEx64 : public Memory64 @@ -233,7 +241,8 @@ class MemoryEx64 : public Memory64 : Memory64(mnem, _machInst, __opClass, _dest, _base), result(_result) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MemoryLiteral64 : public Memory64 @@ -246,7 +255,8 @@ class MemoryLiteral64 : public Memory64 : Memory64(mnem, _machInst, __opClass, _dest, INTREG_ZERO), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; } diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh index 5c387a500..a036b2e11 100644 --- a/src/arch/arm/insts/misc.hh +++ b/src/arch/arm/insts/misc.hh @@ -52,7 +52,8 @@ class MrsOp : public PredOp PredOp(mnem, _machInst, __opClass), dest(_dest) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MsrBase : public PredOp @@ -78,7 +79,8 @@ class MsrImmOp : public MsrBase MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MsrRegOp : public MsrBase @@ -91,7 +93,8 @@ class MsrRegOp : public MsrBase MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MrrcOp : public PredOp @@ -109,7 +112,8 @@ class MrrcOp : public PredOp dest2(_dest2), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class McrrOp : public PredOp @@ -127,7 +131,8 @@ class McrrOp : public PredOp dest(_dest), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class ImmOp : public PredOp @@ -140,7 +145,8 @@ class ImmOp : public PredOp PredOp(mnem, _machInst, __opClass), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegImmOp : public PredOp @@ -154,7 +160,8 @@ class RegImmOp : public PredOp PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegRegOp : public PredOp @@ -168,7 +175,8 @@ class RegRegOp : public PredOp PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegImmRegOp : public PredOp @@ -184,7 +192,8 @@ class RegImmRegOp : public PredOp dest(_dest), imm(_imm), op1(_op1) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegRegRegImmOp : public PredOp @@ -202,7 +211,8 @@ class RegRegRegImmOp : public PredOp dest(_dest), op1(_op1), op2(_op2), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegRegRegRegOp : public PredOp @@ -220,7 +230,8 @@ class RegRegRegRegOp : public PredOp dest(_dest), op1(_op1), op2(_op2), op3(_op3) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegRegRegOp : public PredOp @@ -236,7 +247,8 @@ class RegRegRegOp : public PredOp dest(_dest), op1(_op1), op2(_op2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegRegImmOp : public PredOp @@ -253,7 +265,8 @@ class RegRegImmOp : public PredOp dest(_dest), op1(_op1), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MiscRegRegImmOp : public PredOp @@ -270,7 +283,8 @@ class MiscRegRegImmOp : public PredOp dest(_dest), op1(_op1), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegMiscRegImmOp : public PredOp @@ -287,7 +301,8 @@ class RegMiscRegImmOp : public PredOp dest(_dest), op1(_op1), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegImmImmOp : public PredOp @@ -303,7 +318,8 @@ class RegImmImmOp : public PredOp dest(_dest), imm1(_imm1), imm2(_imm2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegRegImmImmOp : public PredOp @@ -321,7 +337,8 @@ class RegRegImmImmOp : public PredOp dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegImmRegShiftOp : public PredOp @@ -341,7 +358,8 @@ class RegImmRegShiftOp : public PredOp shiftAmt(_shiftAmt), shiftType(_shiftType) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class UnknownOp : public PredOp @@ -352,7 +370,8 @@ class UnknownOp : public PredOp PredOp(mnem, _machInst, __opClass) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; #endif diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh index 3b1347651..961df65d8 100644 --- a/src/arch/arm/insts/misc64.hh +++ b/src/arch/arm/insts/misc64.hh @@ -52,7 +52,8 @@ class ImmOp64 : public ArmStaticInst ArmStaticInst(mnem, _machInst, __opClass), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegRegImmImmOp64 : public ArmStaticInst @@ -70,7 +71,8 @@ class RegRegImmImmOp64 : public ArmStaticInst dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegRegRegImmOp64 : public ArmStaticInst @@ -88,7 +90,8 @@ class RegRegRegImmOp64 : public ArmStaticInst dest(_dest), op1(_op1), op2(_op2), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class UnknownOp64 : public ArmStaticInst @@ -99,7 +102,8 @@ class UnknownOp64 : public ArmStaticInst ArmStaticInst(mnem, _machInst, __opClass) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class MiscRegRegImmOp64 : public ArmStaticInst @@ -116,7 +120,8 @@ class MiscRegRegImmOp64 : public ArmStaticInst dest(_dest), op1(_op1), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class RegMiscRegImmOp64 : public ArmStaticInst @@ -133,7 +138,8 @@ class RegMiscRegImmOp64 : public ArmStaticInst dest(_dest), op1(_op1), imm(_imm) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; #endif diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh index ce4d41bac..d2a9f7080 100644 --- a/src/arch/arm/insts/pred_inst.hh +++ b/src/arch/arm/insts/pred_inst.hh @@ -223,7 +223,8 @@ class PredImmOp : public PredOp rotated_carry = bits(rotated_imm, 31); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; /** @@ -243,7 +244,8 @@ class PredIntOp : public PredOp { } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataImmOp : public PredOp @@ -261,7 +263,8 @@ class DataImmOp : public PredOp dest(_dest), op1(_op1), imm(_imm), rotC(_rotC) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataRegOp : public PredOp @@ -279,7 +282,8 @@ class DataRegOp : public PredOp shiftAmt(_shiftAmt), shiftType(_shiftType) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class DataRegRegOp : public PredOp @@ -296,7 +300,8 @@ class DataRegRegOp : public PredOp shiftType(_shiftType) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; /** @@ -327,19 +332,20 @@ class PredMacroOp : public PredOp } StaticInstPtr - fetchMicroop(MicroPC microPC) const + fetchMicroop(MicroPC microPC) const override { assert(microPC < numMicroops); return microOps[microPC]; } Fault - execute(ExecContext *, Trace::InstRecord *) const + execute(ExecContext *, Trace::InstRecord *) const override { panic("Execute method called when it shouldn't!"); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; /** diff --git a/src/arch/arm/insts/pseudo.hh b/src/arch/arm/insts/pseudo.hh index 5fb7499df..ececbbb86 100644 --- a/src/arch/arm/insts/pseudo.hh +++ b/src/arch/arm/insts/pseudo.hh @@ -56,9 +56,11 @@ class DecoderFaultInst : public ArmStaticInst public: DecoderFaultInst(ExtMachInst _machInst); - Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const; + Fault execute(ExecContext *xc, + Trace::InstRecord *traceData) const override; - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; /** @@ -80,10 +82,11 @@ class FailUnimplemented : public ArmStaticInst FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst, const std::string& _fullMnemonic); - Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const; + Fault execute(ExecContext *xc, + Trace::InstRecord *traceData) const override; - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; /** @@ -109,10 +112,11 @@ class WarnUnimplemented : public ArmStaticInst WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst, const std::string& _fullMnemonic); - Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const; + Fault execute(ExecContext *xc, + Trace::InstRecord *traceData) const override; - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; /** @@ -131,10 +135,11 @@ class McrMrcMiscInst : public ArmStaticInst McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, uint64_t _iss, MiscRegIndex _miscReg); - Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const; + Fault execute(ExecContext *xc, + Trace::InstRecord *traceData) const override; - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; @@ -148,10 +153,11 @@ class McrMrcImplDefined : public McrMrcMiscInst McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst, uint64_t _iss, MiscRegIndex _miscReg); - Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const; + Fault execute(ExecContext *xc, + Trace::InstRecord *traceData) const override; - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index 3ed374ab1..69ae58e66 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -188,12 +188,13 @@ class ArmStaticInst : public StaticInst uint64_t imm) const; void - advancePC(PCState &pcState) const + advancePC(PCState &pcState) const override { pcState.advance(); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; static inline uint32_t cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh index caa22376e..ac20643b8 100644 --- a/src/arch/arm/insts/vfp.hh +++ b/src/arch/arm/insts/vfp.hh @@ -890,7 +890,8 @@ class FpCondCompRegOp : public FpOp op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class FpCondSelOp : public FpOp @@ -906,7 +907,8 @@ class FpCondSelOp : public FpOp dest(_dest), op1(_op1), op2(_op2), condCode(_condCode) {} - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class FpRegRegOp : public FpOp @@ -923,7 +925,8 @@ class FpRegRegOp : public FpOp setVfpMicroFlags(mode, flags); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class FpRegImmOp : public FpOp @@ -940,7 +943,8 @@ class FpRegImmOp : public FpOp setVfpMicroFlags(mode, flags); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class FpRegRegImmOp : public FpOp @@ -958,7 +962,8 @@ class FpRegRegImmOp : public FpOp setVfpMicroFlags(mode, flags); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class FpRegRegRegOp : public FpOp @@ -976,7 +981,8 @@ class FpRegRegRegOp : public FpOp setVfpMicroFlags(mode, flags); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class FpRegRegRegCondOp : public FpOp @@ -997,7 +1003,8 @@ class FpRegRegRegCondOp : public FpOp setVfpMicroFlags(mode, flags); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class FpRegRegRegRegOp : public FpOp @@ -1017,7 +1024,8 @@ class FpRegRegRegRegOp : public FpOp setVfpMicroFlags(mode, flags); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; class FpRegRegRegImmOp : public FpOp @@ -1038,7 +1046,8 @@ class FpRegRegRegImmOp : public FpOp setVfpMicroFlags(mode, flags); } - std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; } diff --git a/src/arch/arm/isa/formats/breakpoint.isa b/src/arch/arm/isa/formats/breakpoint.isa index 4db470b1e..4f281e045 100644 --- a/src/arch/arm/isa/formats/breakpoint.isa +++ b/src/arch/arm/isa/formats/breakpoint.isa @@ -63,10 +63,10 @@ output header {{ flags[IsNonSpeculative] = true; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; + generateDisassembly(Addr pc, const SymbolTable *symtab) const override; }; }}; diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa index ebfddb0a6..1165a1e2a 100644 --- a/src/arch/arm/isa/templates/basic.isa +++ b/src/arch/arm/isa/templates/basic.isa @@ -50,7 +50,8 @@ def template BasicDeclare {{ public: /// Constructor. %(class_name)s(ExtMachInst machInst); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, + Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa index 54821e7c8..440adb4c5 100644 --- a/src/arch/arm/isa/templates/branch.isa +++ b/src/arch/arm/isa/templates/branch.isa @@ -43,7 +43,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -72,8 +72,9 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int32_t _imm, ConditionCode _condCode); - Fault execute(ExecContext *, Trace::InstRecord *) const; - ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + ArmISA::PCState branchTarget( + const ArmISA::PCState &branchPC) const override; /// Explicitly import the otherwise hidden branchTarget using StaticInst::branchTarget; @@ -105,7 +106,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -135,7 +136,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, ConditionCode _condCode); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -167,7 +168,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -178,9 +179,10 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -209,8 +211,9 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int32_t imm, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; - ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + ArmISA::PCState branchTarget( + const ArmISA::PCState &branchPC) const override; /// Explicitly import the otherwise hidden branchTarget using StaticInst::branchTarget; diff --git a/src/arch/arm/isa/templates/branch64.isa b/src/arch/arm/isa/templates/branch64.isa index c55d20541..6eadf3c7c 100644 --- a/src/arch/arm/isa/templates/branch64.isa +++ b/src/arch/arm/isa/templates/branch64.isa @@ -43,7 +43,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, int64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -63,7 +63,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int64_t _imm, ConditionCode _condCode); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -84,7 +84,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -104,7 +104,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int64_t imm, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -125,7 +125,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/data64.isa b/src/arch/arm/isa/templates/data64.isa index 85dde6bed..02c0fdd92 100644 --- a/src/arch/arm/isa/templates/data64.isa +++ b/src/arch/arm/isa/templates/data64.isa @@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -68,7 +68,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, int32_t _shiftAmt, ArmShiftType _shiftType); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -94,7 +94,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ArmExtendType _extendType, int32_t _shiftAmt); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -163,7 +163,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -187,7 +187,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -211,7 +211,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint64_t _imm, ConditionCode _condCode, uint8_t _defCc); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -236,7 +236,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode, uint8_t _defCc); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -261,7 +261,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa index b0e3d29fd..37d0608c0 100644 --- a/src/arch/arm/isa/templates/macromem.isa +++ b/src/arch/arm/isa/templates/macromem.isa @@ -53,9 +53,10 @@ def template MicroMemDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -85,9 +86,10 @@ def template MicroMemPairDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _dreg1, RegIndex _dreg2, RegIndex _base, bool _up, uint8_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -134,9 +136,10 @@ def template MicroNeonMemDeclare {{ } } - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -154,7 +157,7 @@ def template MicroSetPCCPSRDeclare {{ IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -189,7 +192,7 @@ def template MicroIntDeclare {{ public: %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, RegIndex _urc); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -251,7 +254,7 @@ def template MicroNeonMixDeclare {{ } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -304,7 +307,7 @@ def template MicroNeonMixLaneDeclare {{ } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -319,7 +322,7 @@ def template MicroIntMovDeclare {{ public: %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; def template MicroIntMovConstructor {{ @@ -350,7 +353,7 @@ def template MicroIntImmDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -390,7 +393,7 @@ def template MicroIntRegDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, RegIndex _urc, int32_t _shiftAmt, ArmShiftType _shiftType); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -412,7 +415,7 @@ def template MicroIntXERegDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, RegIndex _urc, ArmExtendType _type, uint32_t _shiftAmt); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index 38f5d2051..aa63d4b57 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -582,9 +582,10 @@ def template RfeDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _base, int _mode, bool _wb); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -600,9 +601,10 @@ def template SrsDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _regMode, int _mode, bool _wb); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -618,9 +620,10 @@ def template SwapDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _op1, uint32_t _base); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -637,9 +640,10 @@ def template LoadStoreDImmDeclare {{ uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -656,9 +660,10 @@ def template StoreExDImmDeclare {{ uint32_t _result, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -674,12 +679,14 @@ def template LoadStoreImmDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -698,9 +705,10 @@ def template StoreExImmDeclare {{ uint32_t _result, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -719,9 +727,10 @@ def template StoreDRegDeclare {{ int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -739,12 +748,14 @@ def template StoreRegDeclare {{ int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -765,9 +776,10 @@ def template LoadDRegDeclare {{ int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -785,12 +797,14 @@ def template LoadRegDeclare {{ int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -808,12 +822,14 @@ def template LoadImmDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa index a44a3cd25..bb8594cfe 100644 --- a/src/arch/arm/isa/templates/mem64.isa +++ b/src/arch/arm/isa/templates/mem64.isa @@ -259,12 +259,14 @@ def template DCStore64Declare {{ %(class_name)s(ExtMachInst machInst, IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; - - virtual void - annotateFault(ArmFault *fault) { + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; + + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -342,12 +344,14 @@ def template LoadStoreImm64Declare {{ %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base, int64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -364,12 +368,14 @@ def template LoadStoreImmU64Declare {{ bool noAlloc = false, bool exclusive = false, bool acrel = false); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -386,12 +392,14 @@ def template LoadStoreImmDU64Declare {{ int64_t _imm = 0, bool noAlloc = false, bool exclusive = false, bool acrel = false); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -410,9 +418,10 @@ def template StoreImmDEx64Declare {{ IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, int64_t _imm = 0); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -427,12 +436,14 @@ def template LoadStoreReg64Declare {{ IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset, ArmExtendType _type, uint32_t _shiftAmt); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -450,12 +461,14 @@ def template LoadStoreRegU64Declare {{ bool noAlloc = false, bool exclusive = false, bool acrel = false); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -470,12 +483,14 @@ def template LoadStoreRaw64Declare {{ %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -490,12 +505,14 @@ def template LoadStoreEx64Declare {{ %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -509,12 +526,14 @@ def template LoadStoreLit64Declare {{ /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; @@ -530,12 +549,14 @@ def template LoadStoreLitU64Declare {{ bool noAlloc = false, bool exclusive = false, bool acrel = false); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; - virtual void - annotateFault(ArmFault *fault) { + void + annotateFault(ArmFault *fault) override + { %(fa_code)s } }; diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index 6d63b8e14..e57b9e4af 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint8_t _sysM, bool _r); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -104,7 +104,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t _sysM, bool _r); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -132,7 +132,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -158,7 +158,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -185,7 +185,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, MiscRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -215,7 +215,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, MiscRegIndex _dest, uint32_t imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -244,7 +244,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -268,7 +268,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -294,7 +294,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -321,7 +321,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -352,7 +352,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -382,7 +382,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -412,7 +412,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -442,7 +442,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -472,7 +472,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, MiscRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -501,7 +501,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -531,7 +531,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, uint64_t _imm2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -561,7 +561,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -591,7 +591,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1, int32_t _shiftAmt, ArmShiftType _shiftType); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -623,9 +623,10 @@ def template MiscRegRegImmMemOpDeclare {{ %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/misc64.isa b/src/arch/arm/isa/templates/misc64.isa index 3811cb56a..3c830c858 100644 --- a/src/arch/arm/isa/templates/misc64.isa +++ b/src/arch/arm/isa/templates/misc64.isa @@ -45,7 +45,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst,uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -66,7 +66,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, uint64_t _imm2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -92,7 +92,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -117,7 +117,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -141,7 +141,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, MiscRegIndex _op1, uint64_t _imm); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/mult.isa b/src/arch/arm/isa/templates/mult.isa index 87d96f743..96c61fb28 100644 --- a/src/arch/arm/isa/templates/mult.isa +++ b/src/arch/arm/isa/templates/mult.isa @@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _reg0, IntRegIndex _reg1, IntRegIndex _reg2); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _reg0, IntRegIndex _reg1, IntRegIndex _reg2, IntRegIndex _reg3); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa index 5cde08dcf..35bd3865e 100644 --- a/src/arch/arm/isa/templates/neon.isa +++ b/src/arch/arm/isa/templates/neon.isa @@ -71,7 +71,7 @@ class %(class_name)s : public %(base_class)s } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -97,7 +97,7 @@ class %(class_name)s : public %(base_class)s } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -122,7 +122,7 @@ class %(class_name)s : public %(base_class)s } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -145,7 +145,7 @@ class %(class_name)s : public %(base_class)s } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -170,7 +170,7 @@ class %(class_name)s : public %(base_class)s } } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/neon64.isa b/src/arch/arm/isa/templates/neon64.isa index 153933611..26e6d98b5 100644 --- a/src/arch/arm/isa/templates/neon64.isa +++ b/src/arch/arm/isa/templates/neon64.isa @@ -58,7 +58,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -79,7 +79,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -99,7 +99,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -160,7 +160,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -267,9 +267,10 @@ def template MicroNeonMemDeclare64 {{ %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; @@ -477,7 +478,7 @@ def template MicroNeonMixDeclare64 {{ %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -496,7 +497,7 @@ def template MicroNeonMixLaneDeclare64 {{ %(constructor)s; } - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index d2060a7cd..dccdea60a 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -57,7 +57,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC=true); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -96,7 +96,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, int32_t _shiftAmt, ArmShiftType _shiftType); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -141,7 +141,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift, ArmShiftType _shiftType); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa index c5765f21e..c0859e311 100644 --- a/src/arch/arm/isa/templates/vfp.isa +++ b/src/arch/arm/isa/templates/vfp.isa @@ -105,7 +105,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, VfpMicroMode mode = VfpNotAMicroop); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -132,7 +132,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -159,7 +159,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -189,7 +189,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, VfpMicroMode mode = VfpNotAMicroop); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; @@ -220,7 +220,7 @@ class %(class_name)s : public %(base_class)s IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _cond, VfpMicroMode mode = VfpNotAMicroop); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; diff --git a/src/arch/arm/isa/templates/vfp64.isa b/src/arch/arm/isa/templates/vfp64.isa index 64932336f..f228356be 100644 --- a/src/arch/arm/isa/templates/vfp64.isa +++ b/src/arch/arm/isa/templates/vfp64.isa @@ -92,7 +92,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3, VfpMicroMode mode = VfpNotAMicroop); - Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; }; }}; |