3 files changed, 16 insertions, 81 deletions

diff --git a/src/arch/arm/regfile/float_regfile.hh b/src/arch/arm/regfile/float_regfile.hh
index 757f5f0df..fc4515b17 100644
--- a/src/arch/arm/regfile/float_regfile.hh
+++ b/src/arch/arm/regfile/float_regfile.hh
@@ -75,21 +75,12 @@ namespace ArmISA
         Cause_Field = 11
     };
 
-    const int SingleWidth = 32;
-    const int SingleBytes = SingleWidth / 4;
-
-    const int DoubleWidth = 64;
-    const int DoubleBytes = DoubleWidth / 4;
-
-    const int QuadWidth = 128;
-    const int QuadBytes = QuadWidth / 4;
-
     class FloatRegFile
     {
       protected:
           union {
             FloatRegBits qregs[NumFloatRegs];
-            FloatRegVal regs[NumFloatRegs];
+            FloatReg regs[NumFloatRegs];
           };
 
       public:
@@ -107,38 +98,17 @@ namespace ArmISA
             regs[15] = 10.0;
         }
 
-        FloatRegVal readReg(int floatReg, int width)
+        FloatReg readReg(int floatReg)
         {
             return regs[floatReg];
         }
 
-        FloatRegBits readRegBits(int floatReg, int width)
+        FloatRegBits readRegBits(int floatReg)
         {
-            //return qregs[floatReg];
-            switch(width)
-            {
-                case SingleWidth:
-                {
-                    union {
-                        float f;
-                        uint32_t i;
-                    } s;
-                    s.f = (float) regs[floatReg];
-                    return s.i;
-                }
-                case DoubleWidth:
-                {
-                    uint64_t tmp = (qregs[floatReg]<<32|qregs[floatReg]>>32);
-                    return tmp;
-                }
-                default:
-                    panic("Attempted to read a %d bit floating point "
-                        "register!", width);
-
-            }
+            return qregs[floatReg];
         }
 
-        Fault setReg(int floatReg, const FloatRegVal &val, int width)
+        Fault setReg(int floatReg, const FloatReg &val)
         {
             if (floatReg > 7)
                 panic("Writing to a hard-wired FP register");
@@ -146,23 +116,12 @@ namespace ArmISA
             return NoFault;
         }
 
-        Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
+        Fault setRegBits(int floatReg, const FloatRegBits &val)
         {
             if (floatReg > 7)
                 panic("Writing to a hard-wired FP register");
-            switch(width)
-            {
-                case DoubleWidth:
-                {
-                    uint64_t tmp = (val << 32 | val >> 32);
-                    qregs[floatReg] = tmp;
-                    return NoFault;
-                }
-                case SingleWidth:
-                default:
-                    panic("Attempted to write a %d bit floating point "
-                        "register!", width);
-            }
+            qregs[floatReg] = val;
+            return NoFault;
         }
 
         void serialize(std::ostream &os)
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh
index c432c0c28..6eefe5914 100644
--- a/src/arch/arm/regfile/regfile.hh
+++ b/src/arch/arm/regfile/regfile.hh
@@ -57,44 +57,24 @@ namespace ArmISA
             floatRegFile.clear();
         }
 
-        FloatRegVal readFloatReg(int floatReg)
+        FloatReg readFloatReg(int floatReg)
         {
-            return floatRegFile.readReg(floatReg,SingleWidth);
-        }
-
-        FloatRegVal readFloatReg(int floatReg, int width)
-        {
-            return floatRegFile.readReg(floatReg,width);
+            return floatRegFile.readReg(floatReg);
         }
 
         FloatRegBits readFloatRegBits(int floatReg)
         {
-            return floatRegFile.readRegBits(floatReg,SingleWidth);
-        }
-
-        FloatRegBits readFloatRegBits(int floatReg, int width)
-        {
-            return floatRegFile.readRegBits(floatReg,width);
+            return floatRegFile.readRegBits(floatReg);
         }
 
-        void setFloatReg(int floatReg, const FloatRegVal &val)
+        void setFloatReg(int floatReg, const FloatReg &val)
         {
-            floatRegFile.setReg(floatReg, val, SingleWidth);
-        }
-
-        void setFloatReg(int floatReg, const FloatRegVal &val, int width)
-        {
-            floatRegFile.setReg(floatReg, val, width);
+            floatRegFile.setReg(floatReg, val);
         }
 
         void setFloatRegBits(int floatReg, const FloatRegBits &val)
         {
-            floatRegFile.setRegBits(floatReg, val, SingleWidth);
-        }
-
-        void setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
-        {
-            floatRegFile.setRegBits(floatReg, val, width);
+            floatRegFile.setRegBits(floatReg, val);
         }
 
         IntReg readIntReg(int intReg)
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 3a0fdf2a5..82d1c332c 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -120,12 +120,8 @@ namespace ArmISA
     // Need to use 64 bits to make sure that read requests get handled properly
 
     // floating point register file entry type
-    typedef uint32_t FloatReg32;
-    typedef uint64_t FloatReg64;
-    typedef uint64_t FloatRegBits;
-
-    typedef double FloatRegVal;
-    typedef double FloatReg;
+    typedef uint32_t FloatRegBits;
+    typedef float FloatReg;
 
     // cop-0/cop-1 system control register
     typedef uint64_t MiscReg;