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-rw-r--r--src/arch/arm/insts/misc.cc16
-rw-r--r--src/arch/arm/isa.hh16
-rw-r--r--src/arch/arm/isa/insts/data64.isa16
-rw-r--r--src/arch/arm/isa/insts/fp.isa2
-rw-r--r--src/arch/arm/isa/insts/misc.isa18
5 files changed, 47 insertions, 21 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 0114a4aba..059f86f63 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -51,16 +51,16 @@ MrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
ss << ", ";
bool foundPsr = false;
for (unsigned i = 0; i < numSrcRegs(); i++) {
- RegId reg = srcRegIdx(i);
- if (reg.regClass != MiscRegClass) {
+ const RegId& reg = srcRegIdx(i);
+ if (!reg.isMiscReg()) {
continue;
}
- if (reg.regIdx == MISCREG_CPSR) {
+ if (reg.index() == MISCREG_CPSR) {
ss << "cpsr";
foundPsr = true;
break;
}
- if (reg.regIdx == MISCREG_SPSR) {
+ if (reg.index() == MISCREG_SPSR) {
ss << "spsr";
foundPsr = true;
break;
@@ -79,16 +79,16 @@ MsrBase::printMsrBase(std::ostream &os) const
bool apsr = false;
bool foundPsr = false;
for (unsigned i = 0; i < numDestRegs(); i++) {
- RegId reg = destRegIdx(i);
- if (reg.regClass != MiscRegClass) {
+ const RegId& reg = destRegIdx(i);
+ if (!reg.isMiscReg()) {
continue;
}
- if (reg.regIdx == MISCREG_CPSR) {
+ if (reg.index() == MISCREG_CPSR) {
os << "cpsr_";
foundPsr = true;
break;
}
- if (reg.regIdx == MISCREG_SPSR) {
+ if (reg.index() == MISCREG_SPSR) {
if (bits(byteMask, 1, 0)) {
os << "spsr_";
} else {
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index e05f0e18a..8de90dc93 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -177,6 +177,22 @@ namespace ArmISA
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
void setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc);
+ RegId
+ flattenRegId(const RegId& regId) const
+ {
+ switch (regId.classValue()) {
+ case IntRegClass:
+ return RegId(IntRegClass, flattenIntIndex(regId.index()));
+ case FloatRegClass:
+ return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+ case CCRegClass:
+ return RegId(CCRegClass, flattenCCIndex(regId.index()));
+ case MiscRegClass:
+ return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+ }
+ return RegId();
+ }
+
int
flattenIntIndex(int reg) const
{
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index d60dc60f1..48fc87ccb 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -328,7 +328,7 @@ let {{
buildDataXImmInst("mrs", '''
MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
- flattenMiscIndex(op1);
+ flattenRegId(RegId(MiscRegClass, op1)).index();
CPSR cpsr = Cpsr;
ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
%s
@@ -346,7 +346,7 @@ let {{
buildDataXImmInst("msr", '''
MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
- flattenMiscIndex(dest);
+ flattenRegId(RegId(MiscRegClass, dest)).index();
CPSR cpsr = Cpsr;
ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
%s
@@ -362,7 +362,8 @@ let {{
''')
msrdczva_ea_code = '''
- MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest);
+ MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->flattenRegId(
+ RegId(MiscRegClass, dest)).index();
CPSR cpsr = Cpsr;
ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
'''
@@ -391,7 +392,8 @@ let {{
buildDataXImmInst("msrSP", '''
if (!canWriteAArch64SysReg(
- (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
+ (MiscRegIndex) xc->tcBase()->flattenRegId(
+ RegId(MiscRegClass, dest)).index(),
Scr64, Cpsr, xc->tcBase())) {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
@@ -401,7 +403,8 @@ let {{
buildDataXImmInst("msrDAIFSet", '''
if (!canWriteAArch64SysReg(
- (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
+ (MiscRegIndex) xc->tcBase()->flattenRegId(
+ RegId(MiscRegClass, dest)).index(),
Scr64, Cpsr, xc->tcBase())) {
return std::make_shared<UndefinedInstruction>(
machInst, 0, EC_TRAPPED_MSR_MRS_64,
@@ -414,7 +417,8 @@ let {{
buildDataXImmInst("msrDAIFClr", '''
if (!canWriteAArch64SysReg(
- (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest),
+ (MiscRegIndex) xc->tcBase()->flattenRegId(
+ RegId(MiscRegClass, dest)).index(),
Scr64, Cpsr, xc->tcBase())) {
return std::make_shared<UndefinedInstruction>(
machInst, 0, EC_TRAPPED_MSR_MRS_64,
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index dc2f30701..dff906755 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -224,7 +224,7 @@ let {{
if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
HCR hcr = Hcr;
bool hypTrap = false;
- switch(xc->tcBase()->flattenMiscIndex(op1)) {
+ switch(xc->tcBase()->flattenRegId(RegId(MiscRegClass, op1)).index()) {
case MISCREG_FPSID:
hypTrap = hcr.tid0;
break;
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 6d6e56b8f..5eda615b5 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -813,7 +813,8 @@ let {{
exec_output += PredOpExecute.subst(bfiIop)
mrc14code = '''
- MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(op1);
+ MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
+ RegId(MiscRegClass, op1)).index();
bool can_read, undefined;
std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
if (!can_read || undefined) {
@@ -837,7 +838,8 @@ let {{
mcr14code = '''
- MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest);
+ MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
+ RegId(MiscRegClass, dest)).index();
bool can_write, undefined;
std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
if (undefined || !can_write) {
@@ -862,7 +864,8 @@ let {{
mrc15code = '''
int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
- xc->tcBase()->flattenMiscIndex(preFlatOp1);
+ xc->tcBase()->flattenRegId(RegId(MiscRegClass,
+ preFlatOp1)).index();
bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
Hcptr, imm);
bool can_read, undefined;
@@ -893,7 +896,8 @@ let {{
mcr15code = '''
int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
- xc->tcBase()->flattenMiscIndex(preFlatDest);
+ xc->tcBase()->flattenRegId(RegId(MiscRegClass,
+ preFlatDest)).index();
bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr,
Hcptr, imm);
bool can_write, undefined;
@@ -925,7 +929,8 @@ let {{
mrrc15code = '''
int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
- xc->tcBase()->flattenMiscIndex(preFlatOp1);
+ xc->tcBase()->flattenRegId(RegId(MiscRegClass,
+ preFlatOp1)).index();
bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
bool can_read, undefined;
std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr);
@@ -955,7 +960,8 @@ let {{
mcrr15code = '''
int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
- xc->tcBase()->flattenMiscIndex(preFlatDest);
+ xc->tcBase()->flattenRegId(RegId(MiscRegClass,
+ preFlatDest)).index();
bool hypTrap = mcrrMrrc15TrapToHyp(miscReg, Cpsr, Scr, Hstr, Hcr, imm);
bool can_write, undefined;
std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr);
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-03 03:54:53 +0000