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-rw-r--r--src/arch/arm/insts/vfp.cc2
-rw-r--r--src/arch/arm/isa/formats/fp.isa8
2 files changed, 0 insertions, 10 deletions
diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc
index 6e15282f8..015247d68 100644
--- a/src/arch/arm/insts/vfp.cc
+++ b/src/arch/arm/insts/vfp.cc
@@ -995,7 +995,6 @@ FpOp::binaryOp(FPSCR &fpscr, fpType op1, fpType op2,
// Get NAN behavior right. This varies between x86 and ARM.
if (std::isnan(dest)) {
- const bool single = (sizeof(fpType) == sizeof(float));
const uint64_t qnan =
single ? 0x7fc00000 : ULL(0x7ff8000000000000);
const bool nan1 = std::isnan(op1);
@@ -1066,7 +1065,6 @@ FpOp::unaryOp(FPSCR &fpscr, fpType op1, fpType (*func)(fpType),
// Get NAN behavior right. This varies between x86 and ARM.
if (std::isnan(dest)) {
- const bool single = (sizeof(fpType) == sizeof(float));
const uint64_t qnan =
single ? 0x7fc00000 : ULL(0x7ff8000000000000);
const bool nan = std::isnan(op1);
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 0cb27d7f1..6d779e541 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -1570,13 +1570,6 @@ let {{
}
case 0x6:
if (b == 0xc) {
- const IntRegIndex vd =
- (IntRegIndex)(2 * (bits(machInst, 15, 12) |
- (bits(machInst, 22) << 4)));
- const IntRegIndex vm =
- (IntRegIndex)(2 * (bits(machInst, 3, 0) |
- (bits(machInst, 5) << 4)));
- unsigned size = bits(machInst, 19, 18);
return decodeNeonSTwoShiftUSReg<NVshll>(
size, machInst, vd, vm, 8 << size);
} else {
@@ -1866,7 +1859,6 @@ let {{
case 0x3:
const bool up = (bits(machInst, 23) == 1);
const uint32_t imm = bits(machInst, 7, 0) << 2;
- RegIndex vd;
if (single) {
vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
(bits(machInst, 22)));