diff options
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/ArmTLB.py | 22 | ||||
-rw-r--r-- | src/arch/arm/SConscript | 29 | ||||
-rw-r--r-- | src/arch/arm/faults.cc | 30 | ||||
-rw-r--r-- | src/arch/arm/faults.hh | 17 | ||||
-rw-r--r-- | src/arch/arm/insts/static_inst.hh | 7 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/data.isa | 2 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/m5ops.isa | 8 | ||||
-rw-r--r-- | src/arch/arm/isa/formats/unimp.isa | 9 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/div.isa | 18 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/m5ops.isa | 6 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 51 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/neon.isa | 41 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/swap.isa | 9 | ||||
-rw-r--r-- | src/arch/arm/pagetable.hh | 1 | ||||
-rw-r--r-- | src/arch/arm/remote_gdb.cc | 48 | ||||
-rw-r--r-- | src/arch/arm/tlb.cc | 54 | ||||
-rw-r--r-- | src/arch/arm/tlb.hh | 5 | ||||
-rw-r--r-- | src/arch/arm/utility.cc | 27 |
18 files changed, 159 insertions, 225 deletions
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py index f0d23445f..fc6f51d84 100644 --- a/src/arch/arm/ArmTLB.py +++ b/src/arch/arm/ArmTLB.py @@ -37,26 +37,22 @@ # # Authors: Ali Saidi -from m5.defines import buildEnv from m5.SimObject import SimObject from m5.params import * from m5.proxy import * +from MemObject import MemObject -if buildEnv['FULL_SYSTEM']: - from MemObject import MemObject - - class ArmTableWalker(MemObject): - type = 'ArmTableWalker' - cxx_class = 'ArmISA::TableWalker' - port = Port("Port for TableWalker to do walk the translation with") - sys = Param.System(Parent.any, "system object parameter") - min_backoff = Param.Tick(0, "Minimum backoff delay after failed send") - max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send") +class ArmTableWalker(MemObject): + type = 'ArmTableWalker' + cxx_class = 'ArmISA::TableWalker' + port = Port("Port for TableWalker to do walk the translation with") + sys = Param.System(Parent.any, "system object parameter") + min_backoff = Param.Tick(0, "Minimum backoff delay after failed send") + max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send") class ArmTLB(SimObject): type = 'ArmTLB' cxx_class = 'ArmISA::TLB' size = Param.Int(64, "TLB size") - if buildEnv['FULL_SYSTEM']: - walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker") + walker = Param.ArmTableWalker(ArmTableWalker(), "HW Table walker") diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index a907e52fb..171c04718 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -54,35 +54,32 @@ if env['TARGET_ISA'] == 'arm': Source('insts/pred_inst.cc') Source('insts/static_inst.cc') Source('insts/vfp.cc') + Source('interrupts.cc') Source('isa.cc') + Source('linux/linux.cc') + Source('linux/process.cc') + Source('linux/system.cc') Source('miscregs.cc') - Source('predecoder.cc') Source('nativetrace.cc') + Source('predecoder.cc') + Source('process.cc') + Source('remote_gdb.cc') + Source('stacktrace.cc') + Source('system.cc') + Source('table_walker.cc') Source('tlb.cc') Source('utility.cc') - Source('remote_gdb.cc') + Source('vtophys.cc') + SimObject('ArmInterrupts.py') SimObject('ArmNativeTrace.py') + SimObject('ArmSystem.py') SimObject('ArmTLB.py') DebugFlag('Arm') DebugFlag('TLBVerbose') DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi") DebugFlag('Predecoder', "Instructions returned by the predecoder") - if env['FULL_SYSTEM']: - Source('interrupts.cc') - Source('stacktrace.cc') - Source('system.cc') - Source('vtophys.cc') - Source('linux/system.cc') - Source('table_walker.cc') - - SimObject('ArmInterrupts.py') - SimObject('ArmSystem.py') - else: - Source('process.cc') - Source('linux/linux.cc') - Source('linux/process.cc') # Add in files generated by the ISA description. isa_desc_files = env.ISADesc('isa/main.isa') diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 68c5fa0e8..061392f59 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -47,6 +47,7 @@ #include "cpu/base.hh" #include "cpu/thread_context.hh" #include "debug/Faults.hh" +#include "sim/full_system.hh" namespace ArmISA { @@ -94,13 +95,13 @@ ArmFault::getVector(ThreadContext *tc) } -#if FULL_SYSTEM - void ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst) { // ARM ARM B1.6.3 FaultBase::invoke(tc); + if (!FullSystem) + return; countStat()++; SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); @@ -165,16 +166,21 @@ ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst) void Reset::invoke(ThreadContext *tc, StaticInstPtr inst) { - tc->getCpuPtr()->clearInterrupts(); - tc->clearArchRegs(); + if (FullSystem) { + tc->getCpuPtr()->clearInterrupts(); + tc->clearArchRegs(); + } ArmFault::invoke(tc, inst); } -#else - void UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) { + if (FullSystem) { + ArmFault::invoke(tc, inst); + return; + } + // If the mnemonic isn't defined this has to be an unknown instruction. assert(unknown || mnemonic != NULL); if (disabled) { @@ -192,6 +198,11 @@ UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst) void SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst) { + if (FullSystem) { + ArmFault::invoke(tc, inst); + return; + } + // As of now, there isn't a 32 bit thumb version of this instruction. assert(!machInst.bigThumb); uint32_t callNum; @@ -205,8 +216,6 @@ SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst) tc->pcState(pc); } -#endif // FULL_SYSTEM - template<class T> void AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst) @@ -245,13 +254,14 @@ template void AbortFault<DataAbort>::invoke(ThreadContext *tc, void ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) { DPRINTF(Faults, "Invoking ArmSev Fault\n"); -#if FULL_SYSTEM + if (!FullSystem) + return; + // Set sev_mailbox to 1, clear the pending interrupt from remote // SEV execution and let pipeline continue as pcState is still // valid. tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); tc->getCpuPtr()->clearInterrupt(INT_SEV, 0); -#endif } // return via SUBS pc, lr, xxx; rfe, movs, ldm diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index 2d025cc94..9858e52ef 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -48,8 +48,8 @@ #include "arch/arm/miscregs.hh" #include "arch/arm/types.hh" #include "base/misc.hh" -#include "config/full_system.hh" #include "sim/faults.hh" +#include "sim/full_system.hh" // The design of the "name" and "vect" functions is in sim/faults.hh @@ -108,10 +108,8 @@ class ArmFault : public FaultBase FaultStat count; }; -#if FULL_SYSTEM void invoke(ThreadContext *tc, StaticInstPtr inst = StaticInst::nullStaticInstPtr); -#endif virtual FaultStat& countStat() = 0; virtual FaultOffset offset() = 0; virtual OperatingMode nextMode() = 0; @@ -139,19 +137,14 @@ class ArmFaultVals : public ArmFault }; class Reset : public ArmFaultVals<Reset> -#if FULL_SYSTEM { public: void invoke(ThreadContext *tc, StaticInstPtr inst = StaticInst::nullStaticInstPtr); }; -#else -{}; -#endif //FULL_SYSTEM class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> { -#if !FULL_SYSTEM protected: ExtMachInst machInst; bool unknown; @@ -167,25 +160,27 @@ class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> mnemonic(_mnemonic), disabled(_disabled) { } + UndefinedInstruction() : + machInst(0), unknown(false), mnemonic("undefined"), disabled(false) + {} void invoke(ThreadContext *tc, StaticInstPtr inst = StaticInst::nullStaticInstPtr); -#endif }; class SupervisorCall : public ArmFaultVals<SupervisorCall> { -#if !FULL_SYSTEM protected: ExtMachInst machInst; public: SupervisorCall(ExtMachInst _machInst) : machInst(_machInst) {} + SupervisorCall() : machInst(0) + {} void invoke(ThreadContext *tc, StaticInstPtr inst = StaticInst::nullStaticInstPtr); -#endif }; template <class T> diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh index 5af97b796..c36024ecd 100644 --- a/src/arch/arm/insts/static_inst.hh +++ b/src/arch/arm/insts/static_inst.hh @@ -47,6 +47,7 @@ #include "base/trace.hh" #include "cpu/static_inst.hh" #include "sim/byteswap.hh" +#include "sim/full_system.hh" namespace ArmISA { @@ -295,11 +296,11 @@ class ArmStaticInst : public StaticInst inline Fault disabledFault() const { -#if FULL_SYSTEM + if (FullSystem) { return new UndefinedInstruction(); -#else + } else { return new UndefinedInstruction(machInst, false, mnemonic, true); -#endif + } } }; } diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa index 03a585001..ffe5f45e3 100644 --- a/src/arch/arm/isa/formats/data.isa +++ b/src/arch/arm/isa/formats/data.isa @@ -1103,7 +1103,6 @@ def format ArmMisc() {{ switch (IMM) { case 0x0: return new NopInst(machInst); -#if FULL_SYSTEM case 0x1: return new YieldInst(machInst); case 0x2: @@ -1112,7 +1111,6 @@ def format ArmMisc() {{ return new WfiInst(machInst); case 0x4: return new SevInst(machInst); -#endif default: return new Unknown(machInst); } diff --git a/src/arch/arm/isa/formats/m5ops.isa b/src/arch/arm/isa/formats/m5ops.isa index 534d12cd9..1eb7d3f65 100644 --- a/src/arch/arm/isa/formats/m5ops.isa +++ b/src/arch/arm/isa/formats/m5ops.isa @@ -42,36 +42,28 @@ def format M5ops() {{ { const uint32_t m5func = bits(machInst, 23, 16); switch(m5func) { -#if FULL_SYSTEM case 0x00: return new Arm(machInst); case 0x01: return new Quiesce(machInst); case 0x02: return new QuiesceNs(machInst); case 0x03: return new QuiesceCycles(machInst); case 0x04: return new QuiesceTime(machInst); -#endif case 0x07: return new Rpns(machInst); case 0x09: return new WakeCPU(machInst); case 0x10: return new Deprecated_ivlb(machInst); case 0x11: return new Deprecated_ivle(machInst); case 0x20: return new Deprecated_exit (machInst); case 0x21: return new M5exit(machInst); -#if FULL_SYSTEM case 0x31: return new Loadsymbol(machInst); case 0x30: return new Initparam(machInst); -#endif case 0x40: return new Resetstats(machInst); case 0x41: return new Dumpstats(machInst); case 0x42: return new Dumpresetstats(machInst); case 0x43: return new M5checkpoint(machInst); -#if FULL_SYSTEM case 0x4F: return new M5writefile(machInst); case 0x50: return new M5readfile(machInst); -#endif case 0x51: return new M5break(machInst); case 0x52: return new M5switchcpu(machInst); -#if FULL_SYSTEM case 0x53: return new M5addsymbol(machInst); -#endif case 0x54: return new M5panic(machInst); case 0x5a: return new M5workbegin(machInst); case 0x5b: return new M5workend(machInst); diff --git a/src/arch/arm/isa/formats/unimp.isa b/src/arch/arm/isa/formats/unimp.isa index a0e0afd32..1c9a4b402 100644 --- a/src/arch/arm/isa/formats/unimp.isa +++ b/src/arch/arm/isa/formats/unimp.isa @@ -147,11 +147,10 @@ output exec {{ FailUnimplemented::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(machInst, false, mnemonic); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(machInst, false, mnemonic); } Fault diff --git a/src/arch/arm/isa/insts/div.isa b/src/arch/arm/isa/insts/div.isa index 8a94d1ebd..1ff6ef9e4 100644 --- a/src/arch/arm/isa/insts/div.isa +++ b/src/arch/arm/isa/insts/div.isa @@ -41,11 +41,10 @@ let {{ sdivCode = ''' if (Op2_sw == 0) { if (((SCTLR)Sctlr).dz) { -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); } Dest_sw = 0; } else if (Op1_sw == INT_MIN && Op2_sw == -1) { @@ -65,11 +64,10 @@ let {{ udivCode = ''' if (Op2_uw == 0) { if (((SCTLR)Sctlr).dz) { -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); } Dest_uw = 0; } else { diff --git a/src/arch/arm/isa/insts/m5ops.isa b/src/arch/arm/isa/insts/m5ops.isa index 1a154459e..a32bf6dfc 100644 --- a/src/arch/arm/isa/insts/m5ops.isa +++ b/src/arch/arm/isa/insts/m5ops.isa @@ -190,13 +190,9 @@ let {{ exec_output += PredOpExecute.subst(loadsymbolIop) initparamCode = ''' -#if FULL_SYSTEM uint64_t ip_val = PseudoInst::initParam(xc->tcBase()); R0 = bits(ip_val, 31, 0); R1 = bits(ip_val, 63, 32); -#else - PseudoInst::panicFsOnlyPseudoInst("initparam"); -#endif ''' initparamIop = InstObjParams("initparam", "Initparam", "PredOp", @@ -266,14 +262,12 @@ let {{ exec_output += PredOpExecute.subst(m5readfileIop) m5writefileCode = ''' -#if FULL_SYSTEM int n = 4; uint64_t offset = getArgument(xc->tcBase(), n, sizeof(uint64_t), false); n = 6; Addr filenameAddr = getArgument(xc->tcBase(), n, sizeof(Addr), false); R0 = PseudoInst::writefile(xc->tcBase(), R0, join32to64(R3,R2), offset, filenameAddr); -#endif ''' m5writefileIop = InstObjParams("m5writefile", "M5writefile", "PredOp", { "code": m5writefileCode, diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 45d5d8d32..d8ee5e88d 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -40,11 +40,11 @@ let {{ svcCode = ''' -#if FULL_SYSTEM - fault = new SupervisorCall; -#else - fault = new SupervisorCall(machInst); -#endif + if (FullSystem) { + fault = new SupervisorCall; + } else { + fault = new SupervisorCall(machInst); + } ''' svcIop = InstObjParams("svc", "Svc", "PredOp", @@ -502,7 +502,6 @@ let {{ exec_output += PredOpExecute.subst(yieldIop) wfeCode = ''' -#if FULL_SYSTEM // WFE Sleeps if SevMailbox==0 and no unmasked interrupts are pending if (SevMailbox == 1) { SevMailbox = 0; @@ -512,14 +511,11 @@ let {{ } else { PseudoInst::quiesce(xc->tcBase()); } -#endif ''' wfePredFixUpCode = ''' -#if FULL_SYSTEM // WFE is predicated false, reset SevMailbox to reduce spurious sleeps // and SEV interrupts SevMailbox = 1; -#endif ''' wfeIop = InstObjParams("wfe", "WfeInst", "PredOp", \ { "code" : wfeCode, @@ -532,14 +528,12 @@ let {{ exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop) wfiCode = ''' -#if FULL_SYSTEM // WFI doesn't sleep if interrupts are pending (masked or not) if (xc->tcBase()->getCpuPtr()->getInterruptController()->checkRaw()) { PseudoInst::quiesceSkip(xc->tcBase()); } else { PseudoInst::quiesce(xc->tcBase()); } -#endif ''' wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \ { "code" : wfiCode, "predicate_test" : predicateTest }, @@ -550,7 +544,6 @@ let {{ exec_output += QuiescePredOpExecute.subst(wfiIop) sevCode = ''' -#if FULL_SYSTEM SevMailbox = 1; System *sys = xc->tcBase()->getSystemPtr(); for (int x = 0; x < sys->numContexts(); x++) { @@ -563,7 +556,6 @@ let {{ oc->getCpuPtr()->postInterrupt(INT_SEV, 0); } } -#endif ''' sevIop = InstObjParams("sev", "SevInst", "PredOp", \ { "code" : sevCode, "predicate_test" : predicateTest }, @@ -580,11 +572,10 @@ let {{ decoder_output += BasicConstructor.subst(itIop) exec_output += PredOpExecute.subst(itIop) unknownCode = ''' -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(machInst, true); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(machInst, true); ''' unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \ { "code": unknownCode, @@ -637,12 +628,12 @@ let {{ mrc15code = ''' CPSR cpsr = Cpsr; - if (cpsr.mode == MODE_USER) -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (cpsr.mode == MODE_USER) { + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); + } Dest = MiscOp1; ''' @@ -656,12 +647,12 @@ let {{ mcr15code = ''' CPSR cpsr = Cpsr; - if (cpsr.mode == MODE_USER) -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (cpsr.mode == MODE_USER) { + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); + } MiscDest = Op1; ''' mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp", diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index dd0d49a5c..b1ad1eeb3 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -872,11 +872,10 @@ let {{ readDestCode = 'destElem = gtoh(destReg.elements[i]);' eWalkCode += ''' if (imm < 0 && imm >= eCount) { -#if FULL_SYSTEM - fault = new UndefinedInstruction; -#else - fault = new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + fault = new UndefinedInstruction; + else + fault = new UndefinedInstruction(false, mnemonic); } else { for (unsigned i = 0; i < eCount; i++) { Element srcElem1 = gtoh(srcReg1.elements[i]); @@ -927,11 +926,10 @@ let {{ readDestCode = 'destElem = gtoh(destReg.elements[i]);' eWalkCode += ''' if (imm < 0 && imm >= eCount) { -#if FULL_SYSTEM - fault = new UndefinedInstruction; -#else - fault = new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + fault = new UndefinedInstruction; + else + fault = new UndefinedInstruction(false, mnemonic); } else { for (unsigned i = 0; i < eCount; i++) { Element srcElem1 = gtoh(srcReg1.elements[i]); @@ -980,11 +978,10 @@ let {{ readDestCode = 'destReg = destRegs[i];' eWalkCode += ''' if (imm < 0 && imm >= eCount) { -#if FULL_SYSTEM - fault = new UndefinedInstruction; -#else - fault = new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + fault = new UndefinedInstruction; + else + fault = new UndefinedInstruction(false, mnemonic); } else { for (unsigned i = 0; i < rCount; i++) { FloatReg srcReg1 = srcRegs1[i]; @@ -3296,14 +3293,14 @@ let {{ destReg.elements[i] = srcReg1.elements[index]; } else { index -= eCount; - if (index >= eCount) -#if FULL_SYSTEM - fault = new UndefinedInstruction; -#else - fault = new UndefinedInstruction(false, mnemonic); -#endif - else + if (index >= eCount) { + if (FullSystem) + fault = new UndefinedInstruction; + else + fault = new UndefinedInstruction(false, mnemonic); + } else { destReg.elements[i] = srcReg2.elements[index]; + } } } ''' diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa index f319e75aa..b42a1c4b2 100644 --- a/src/arch/arm/isa/insts/swap.isa +++ b/src/arch/arm/isa/insts/swap.isa @@ -73,11 +73,10 @@ let {{ swpPreAccCode = ''' if (!((SCTLR)Sctlr).sw) { -#if FULL_SYSTEM - return new UndefinedInstruction; -#else - return new UndefinedInstruction(false, mnemonic); -#endif + if (FullSystem) + return new UndefinedInstruction; + else + return new UndefinedInstruction(false, mnemonic); } ''' diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh index 6d84fbf7b..2c86d3d84 100644 --- a/src/arch/arm/pagetable.hh +++ b/src/arch/arm/pagetable.hh @@ -46,7 +46,6 @@ #include "arch/arm/isa_traits.hh" #include "arch/arm/utility.hh" #include "arch/arm/vtophys.hh" -#include "config/full_system.hh" #include "sim/serialize.hh" namespace ArmISA { diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc index 223ff4c69..528e19acf 100644 --- a/src/arch/arm/remote_gdb.cc +++ b/src/arch/arm/remote_gdb.cc @@ -134,11 +134,6 @@ #include <string> -#include "config/full_system.hh" -#if FULL_SYSTEM -#include "arch/arm/vtophys.hh" -#endif - #include "arch/arm/pagetable.hh" #include "arch/arm/registers.hh" #include "arch/arm/remote_gdb.hh" @@ -157,6 +152,7 @@ #include "mem/page_table.hh" #include "mem/physical.hh" #include "mem/port.hh" +#include "sim/full_system.hh" #include "sim/system.hh" using namespace std; @@ -173,28 +169,28 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc) bool RemoteGDB::acc(Addr va, size_t len) { -#if FULL_SYSTEM - Addr last_va; - va = truncPage(va); - last_va = roundPage(va + len); - - do { - if (virtvalid(context, va)) { - return true; - } - va += PageBytes; - } while (va < last_va); - - DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); - return true; -#else - TlbEntry entry; - //Check to make sure the first byte is mapped into the processes address - //space. - if (context->getProcessPtr()->pTable->lookup(va, entry)) + if (FullSystem) { + Addr last_va; + va = truncPage(va); + last_va = roundPage(va + len); + + do { + if (virtvalid(context, va)) { + return true; + } + va += PageBytes; + } while (va < last_va); + + DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va); return true; - return false; -#endif + } else { + TlbEntry entry; + //Check to make sure the first byte is mapped into the processes address + //space. + if (context->getProcessPtr()->pTable->lookup(va, entry)) + return true; + return false; + } } /* diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index f4dc47655..0b003e9fb 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -47,6 +47,8 @@ #include "arch/arm/faults.hh" #include "arch/arm/pagetable.hh" +#include "arch/arm/system.hh" +#include "arch/arm/table_walker.hh" #include "arch/arm/tlb.hh" #include "arch/arm/utility.hh" #include "base/inifile.hh" @@ -58,29 +60,20 @@ #include "debug/TLBVerbose.hh" #include "mem/page_table.hh" #include "params/ArmTLB.hh" +#include "sim/full_system.hh" #include "sim/process.hh" -#if FULL_SYSTEM -#include "arch/arm/system.hh" -#include "arch/arm/table_walker.hh" -#endif - using namespace std; using namespace ArmISA; TLB::TLB(const Params *p) - : BaseTLB(p), size(p->size) -#if FULL_SYSTEM - , tableWalker(p->walker) -#endif - , rangeMRU(1), bootUncacheability(false), miscRegValid(false) + : BaseTLB(p), size(p->size) , tableWalker(p->walker), + rangeMRU(1), bootUncacheability(false), miscRegValid(false) { table = new TlbEntry[size]; memset(table, 0, sizeof(TlbEntry) * size); -#if FULL_SYSTEM tableWalker->setTlb(this); -#endif } TLB::~TLB() @@ -404,7 +397,6 @@ TLB::regStats() accesses = readAccesses + writeAccesses + instAccesses; } -#if !FULL_SYSTEM Fault TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing) @@ -436,8 +428,6 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, return NoFault; } -#else // FULL_SYSTEM - Fault TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp) { @@ -581,7 +571,6 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, } } - if (!bootUncacheability && ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr)) req->setFlags(Request::UNCACHEABLE); @@ -687,18 +676,15 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, return NoFault; } -#endif - Fault TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) { bool delay = false; Fault fault; -#if FULL_SYSTEM - fault = translateFs(req, tc, mode, NULL, delay, false); -#else - fault = translateSe(req, tc, mode, NULL, delay, false); -#endif + if (FullSystem) + fault = translateFs(req, tc, mode, NULL, delay, false); + else + fault = translateSe(req, tc, mode, NULL, delay, false); assert(!delay); return fault; } @@ -708,11 +694,10 @@ TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) { bool delay = false; Fault fault; -#if FULL_SYSTEM - fault = translateFs(req, tc, mode, NULL, delay, false, true); -#else - fault = translateSe(req, tc, mode, NULL, delay, false); -#endif + if (FullSystem) + fault = translateFs(req, tc, mode, NULL, delay, false, true); + else + fault = translateSe(req, tc, mode, NULL, delay, false); assert(!delay); return fault; } @@ -724,11 +709,10 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc, assert(translation); bool delay = false; Fault fault; -#if FULL_SYSTEM - fault = translateFs(req, tc, mode, translation, delay, true); -#else - fault = translateSe(req, tc, mode, translation, delay, true); -#endif + if (FullSystem) + fault = translateFs(req, tc, mode, translation, delay, true); + else + fault = translateSe(req, tc, mode, translation, delay, true); DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault != NoFault); if (!delay) @@ -741,11 +725,7 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc, Port* TLB::getPort() { -#if FULL_SYSTEM return tableWalker->getPort("port"); -#else - return NULL; -#endif } diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index bdfa2fc9f..daf59f01d 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -89,9 +89,7 @@ class TLB : public BaseTLB uint32_t _attr; // Memory attributes for last accessed TLB entry -#if FULL_SYSTEM TableWalker *tableWalker; -#endif /** Lookup an entry in the TLB * @param vpn virtual address @@ -201,14 +199,11 @@ class TLB : public BaseTLB return _attr; } -#if FULL_SYSTEM Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, bool functional = false); -#else Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing); -#endif Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode); Fault translateTiming(RequestPtr req, ThreadContext *tc, Translation *translation, Mode mode); diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index b31dc4324..0527e135f 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -40,16 +40,13 @@ #include "arch/arm/faults.hh" #include "arch/arm/isa_traits.hh" +#include "arch/arm/tlb.hh" #include "arch/arm/utility.hh" +#include "arch/arm/vtophys.hh" #include "config/use_checker.hh" #include "cpu/thread_context.hh" - -#if FULL_SYSTEM -#include "arch/arm/vtophys.hh" #include "mem/fs_translating_port_proxy.hh" -#endif - -#include "arch/arm/tlb.hh" +#include "sim/full_system.hh" namespace ArmISA { @@ -67,20 +64,24 @@ initCPU(ThreadContext *tc, int cpuId) uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) { -#if FULL_SYSTEM + if (!FullSystem) { + panic("getArgument() only implemented for full system mode.\n"); + M5_DUMMY_RETURN + } + if (size == (uint16_t)(-1)) size = ArmISA::MachineBytes; if (fp) panic("getArgument(): Floating point arguments not implemented\n"); if (number < NumArgumentRegs) { - // If the argument is 64 bits, it must be in an even regiser number - // Increment the number here if it isn't even + // If the argument is 64 bits, it must be in an even regiser + // number. Increment the number here if it isn't even. if (size == sizeof(uint64_t)) { if ((number % 2) != 0) number++; - // Read the two halves of the data - // number is inc here to get the second half of the 64 bit reg + // Read the two halves of the data. Number is inc here to + // get the second half of the 64 bit reg. uint64_t tmp; tmp = tc->readIntReg(number++); tmp |= tc->readIntReg(number) << 32; @@ -106,10 +107,6 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) } return arg; } -#else - panic("getArgument() only implemented for FULL_SYSTEM\n"); - M5_DUMMY_RETURN -#endif } void |