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-rw-r--r--src/arch/arm/tlb.cc16
-rw-r--r--src/arch/arm/tlb.hh1
2 files changed, 17 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 79eef1b8d..521a43226 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -536,6 +536,11 @@ TLB::regStats()
.name(name() + ".prefetch_faults")
.desc("Number of TLB faults due to prefetch")
;
+
+ specTLBMisses
+ .name(name() + ".spec_tlb_misses")
+ .desc("Number of TLB misses from a speculative mem instructions")
+ ;
domainFaults
.name(name() + ".domain_faults")
@@ -1426,6 +1431,17 @@ TLB::getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode,
vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2);
}
+ if (req->isSpec()) {
+ // if the request is a prefetch don't attempt to fill the TLB or go
+ // any further with the memory access (here we can safely use the
+ // fault status for the short desc. format in all cases)
+ specTLBMisses++;
+ //FIXME: currently resue the prefetch tlbmiss fault
+ //do not want to introduce new fault declaration
+ return std::make_shared<PrefetchAbort>(
+ vaddr_tainted, ArmFault::PrefetchTLBMiss, isStage2);
+ }
+
if (is_fetch)
instMisses++;
else if (is_write)
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 336b31b78..9f2acda6c 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -177,6 +177,7 @@ class TLB : public BaseTLB
mutable Stats::Scalar flushedEntries;
mutable Stats::Scalar alignFaults;
mutable Stats::Scalar prefetchFaults;
+ mutable Stats::Scalar specTLBMisses;
mutable Stats::Scalar domainFaults;
mutable Stats::Scalar permsFaults;