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-rw-r--r--src/arch/arm/isa_device.hh4
-rw-r--r--src/arch/arm/kvm/armv8_cpu.hh6
-rw-r--r--src/arch/arm/kvm/base_cpu.hh4
-rw-r--r--src/arch/arm/kvm/gic.hh20
-rw-r--r--src/arch/arm/pagetable.hh4
-rw-r--r--src/arch/arm/pmu.hh16
-rw-r--r--src/arch/arm/table_walker.hh4
-rw-r--r--src/arch/arm/tlb.hh8
-rw-r--r--src/arch/arm/types.hh9
9 files changed, 37 insertions, 38 deletions
diff --git a/src/arch/arm/isa_device.hh b/src/arch/arm/isa_device.hh
index 8b12fa502..185e632a5 100644
--- a/src/arch/arm/isa_device.hh
+++ b/src/arch/arm/isa_device.hh
@@ -97,8 +97,8 @@ class DummyISADevice : public BaseISADevice
: BaseISADevice() {}
~DummyISADevice() {}
- void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
- MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
+ void setMiscReg(int misc_reg, MiscReg val) override;
+ MiscReg readMiscReg(int misc_reg) override;
};
}
diff --git a/src/arch/arm/kvm/armv8_cpu.hh b/src/arch/arm/kvm/armv8_cpu.hh
index 97127b471..aee27a8a4 100644
--- a/src/arch/arm/kvm/armv8_cpu.hh
+++ b/src/arch/arm/kvm/armv8_cpu.hh
@@ -83,11 +83,11 @@ class ArmV8KvmCPU : public BaseArmKvmCPU
ArmV8KvmCPU(ArmV8KvmCPUParams *params);
virtual ~ArmV8KvmCPU();
- void dump() M5_ATTR_OVERRIDE;
+ void dump() override;
protected:
- void updateKvmState() M5_ATTR_OVERRIDE;
- void updateThreadContext() M5_ATTR_OVERRIDE;
+ void updateKvmState() override;
+ void updateThreadContext() override;
protected:
/** Mapping between integer registers in gem5 and KVM */
diff --git a/src/arch/arm/kvm/base_cpu.hh b/src/arch/arm/kvm/base_cpu.hh
index 736153b78..2f6f978f7 100644
--- a/src/arch/arm/kvm/base_cpu.hh
+++ b/src/arch/arm/kvm/base_cpu.hh
@@ -52,10 +52,10 @@ class BaseArmKvmCPU : public BaseKvmCPU
BaseArmKvmCPU(BaseArmKvmCPUParams *params);
virtual ~BaseArmKvmCPU();
- void startup() M5_ATTR_OVERRIDE;
+ void startup() override;
protected:
- Tick kvmRun(Tick ticks) M5_ATTR_OVERRIDE;
+ Tick kvmRun(Tick ticks) override;
/** Cached state of the IRQ line */
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
index 4a115c87c..f156caa6b 100644
--- a/src/arch/arm/kvm/gic.hh
+++ b/src/arch/arm/kvm/gic.hh
@@ -76,23 +76,23 @@ class KvmGic : public BaseGic
KvmGic(const KvmGicParams *p);
~KvmGic();
- void startup() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
- void drainResume() M5_ATTR_OVERRIDE { verifyMemoryMode(); }
+ void startup() override { verifyMemoryMode(); }
+ void drainResume() override { verifyMemoryMode(); }
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(Checkpoint *cp, const std::string &sec) override;
public: // PioDevice
AddrRangeList getAddrRanges() const { return addrRanges; }
- Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE;
- Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE;
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
public: // BaseGic
- void sendInt(uint32_t num) M5_ATTR_OVERRIDE;
- void clearInt(uint32_t num) M5_ATTR_OVERRIDE;
+ void sendInt(uint32_t num) override;
+ void clearInt(uint32_t num) override;
- void sendPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
- void clearPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE;
+ void sendPPInt(uint32_t num, uint32_t cpu) override;
+ void clearPPInt(uint32_t num, uint32_t cpu) override;
protected:
/**
diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh
index 3de993d27..6d306d6e0 100644
--- a/src/arch/arm/pagetable.hh
+++ b/src/arch/arm/pagetable.hh
@@ -284,7 +284,7 @@ struct TlbEntry : public Serializable
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
SERIALIZE_SCALAR(longDescFormat);
SERIALIZE_SCALAR(pfn);
@@ -314,7 +314,7 @@ struct TlbEntry : public Serializable
paramOut(cp, "domain", domain_);
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
UNSERIALIZE_SCALAR(longDescFormat);
UNSERIALIZE_SCALAR(pfn);
diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh
index 80be965a4..fc5bf74b3 100644
--- a/src/arch/arm/pmu.hh
+++ b/src/arch/arm/pmu.hh
@@ -96,10 +96,10 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
void addEventProbe(unsigned int id, SimObject *obj, const char *name);
public: // SimObject and related interfaces
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
public: // ISA Device interface
@@ -109,14 +109,14 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
* @param misc_reg Register number (see miscregs.hh)
* @param val Value to store
*/
- void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
+ void setMiscReg(int misc_reg, MiscReg val) override;
/**
* Read a register within the PMU.
*
* @param misc_reg Register number (see miscregs.hh)
* @return Register value.
*/
- MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
+ MiscReg readMiscReg(int misc_reg) override;
protected: // PMU register types and constants
BitUnion32(PMCR_t)
@@ -269,7 +269,7 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
: ProbeListenerArgBase(pm, name),
pmu(_pmu), id(_id) {}
- void notify(const uint64_t &val) M5_ATTR_OVERRIDE
+ void notify(const uint64_t &val) override
{
pmu.handleEvent(id, val);
}
@@ -329,8 +329,8 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
listeners.reserve(4);
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/**
* Add an event count to the counter and check for overflow.
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index e973e9a74..8af70075d 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -891,8 +891,8 @@ class TableWalker : public MemObject
bool haveLargeAsid64() const { return _haveLargeAsid64; }
/** Checks if all state is cleared and if so, completes drain */
void completeDrain();
- DrainState drain() M5_ATTR_OVERRIDE;
- virtual void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ virtual void drainResume() override;
virtual BaseMasterPort& getMasterPort(const std::string &if_name,
PortID idx = InvalidPortID);
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 35049db48..f6776b0a9 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -284,15 +284,15 @@ class TLB : public BaseTLB
bool callFromS2);
Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void regStats();
- void regProbePoints() M5_ATTR_OVERRIDE;
+ void regProbePoints() override;
/**
* Get the table walker master port. This is used for migrating
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index c54bfb5f4..29828be75 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -45,7 +45,6 @@
#include "arch/generic/types.hh"
#include "base/bitunion.hh"
-#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "debug/Decoder.hh"
@@ -483,7 +482,7 @@ namespace ArmISA
}
void
- serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ serialize(CheckpointOut &cp) const override
{
Base::serialize(cp);
SERIALIZE_SCALAR(flags);
@@ -494,7 +493,7 @@ namespace ArmISA
}
void
- unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ unserialize(CheckpointIn &cp) override
{
Base::unserialize(cp);
UNSERIALIZE_SCALAR(flags);
@@ -740,7 +739,7 @@ namespace ArmISA
} // namespace ArmISA
-__hash_namespace_begin
+namespace std {
template<>
struct hash<ArmISA::ExtMachInst> :
@@ -752,6 +751,6 @@ struct hash<ArmISA::ExtMachInst> :
};
-__hash_namespace_end
+}
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 18:31:29 +0000