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-rw-r--r--src/arch/arm/tlb.cc11
-rw-r--r--src/arch/arm/tlb.hh4
2 files changed, 12 insertions, 3 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index e7ac935e6..170d819d8 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -253,6 +253,14 @@ TLB::flushMva(Addr mva)
}
void
+TLB::drainResume()
+{
+ // We might have unserialized something or switched CPUs, so make
+ // sure to re-read the misc regs.
+ miscRegValid = false;
+}
+
+void
TLB::serialize(ostream &os)
{
DPRINTF(Checkpoint, "Serializing Arm TLB\n");
@@ -278,7 +286,6 @@ TLB::unserialize(Checkpoint *cp, const string &section)
for(int i = 0; i < min(size, num_entries); i++){
table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i));
}
- miscRegValid = false;
}
void
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 968699764..f5c7320ed 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -208,6 +208,8 @@ class TLB : public BaseTLB
Fault translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);
+ void drainResume();
+
// Checkpointing
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);