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-rw-r--r--src/arch/arm/isa/insts/fp64.isa8
-rw-r--r--src/arch/arm/isa/insts/neon64.isa24
-rw-r--r--src/arch/arm/isa/operands.isa293
-rw-r--r--src/arch/arm/isa/templates/mem.isa10
-rw-r--r--src/arch/arm/isa/templates/pred.isa6
5 files changed, 241 insertions, 100 deletions
diff --git a/src/arch/arm/isa/insts/fp64.isa b/src/arch/arm/isa/insts/fp64.isa
index 706f77fb0..a5e1085de 100644
--- a/src/arch/arm/isa/insts/fp64.isa
+++ b/src/arch/arm/isa/insts/fp64.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2012-2013 ARM Limited
+// Copyright (c) 2012-2013, 2016 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -123,9 +123,11 @@ let {{
exec_output += BasicExecute.subst(fmovCoreRegXIop);
fmovUCoreRegXCode = vfp64EnabledCheckCode + '''
+ /* Explicitly merge with previous value */
+ AA64FpDestP0_uw = AA64FpDestP0_uw;
+ AA64FpDestP1_uw = AA64FpDestP1_uw;
AA64FpDestP2_uw = XOp1_ud;
- AA64FpDestP3_uw = XOp1_ud >> 32;
- '''
+ AA64FpDestP3_uw = XOp1_ud >> 32;'''
fmovUCoreRegXIop = InstObjParams("fmov", "FmovUCoreRegX", "FpRegRegOp",
{ "code": fmovUCoreRegXCode,
"op_class": "FloatMiscOp" }, [])
diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa
index 7c9040be3..4897e7c91 100644
--- a/src/arch/arm/isa/insts/neon64.isa
+++ b/src/arch/arm/isa/insts/neon64.isa
@@ -1,6 +1,6 @@
// -*- mode: c++ -*-
-// Copyright (c) 2012-2013, 2015 ARM Limited
+// Copyright (c) 2012-2013, 2015-2016 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -225,11 +225,16 @@ let {{
AA64FpDestP%(destReg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg, "destReg": destReg }
destReg += 1
- if destCnt < 4 and not hi: # zero upper half
- for reg in range(destCnt, 4):
- eWalkCode += '''
- AA64FpDestP%(reg)d_uw = 0;
- ''' % { "reg" : reg }
+ if destCnt < 4:
+ if hi: # Explicitly merge with lower half
+ for reg in range(0, destCnt):
+ eWalkCode += '''
+ AA64FpDestP%(reg)d_uw = AA64FpDestP%(reg)d_uw;''' % { "reg" : reg }
+ else: # zero upper half
+ for reg in range(destCnt, 4):
+ eWalkCode += '''
+ AA64FpDestP%(reg)d_uw = 0;''' % { "reg" : reg }
+
iop = InstObjParams(name, Name,
"DataX2RegImmOp" if byElem else "DataX2RegOp",
{ "code": eWalkCode,
@@ -429,11 +434,16 @@ let {{
AA64FpDestP%(destReg)d_uw = gtoh(destReg.regs[%(reg)d]);
''' % { "reg" : reg, "destReg": destReg }
destReg += 1
- if not hi:
+ if hi:
+ for reg in range(0, 2): # Explicitly merge with the lower half
+ eWalkCode += '''
+ AA64FpDestP%(reg)d_uw = AA64FpDestP%(reg)d_uw;''' % { "reg" : reg }
+ else:
for reg in range(2, 4): # zero upper half
eWalkCode += '''
AA64FpDestP%(reg)d_uw = 0;
''' % { "reg" : reg }
+
iop = InstObjParams(name, Name,
"DataX1RegImmOp" if hasImm else "DataX1RegOp",
{ "code": eWalkCode,
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index e48c154d4..5898075ab 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -1,5 +1,5 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010-2014 ARM Limited
+// Copyright (c) 2010-2014, 2016 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -49,7 +49,10 @@ def operand_types {{
'ud' : 'uint64_t',
'tud' : 'Twin64_t',
'sf' : 'float',
- 'df' : 'double'
+ 'df' : 'double',
+ 'vc' : 'TheISA::VecRegContainer',
+ # For operations that are implemented as a template
+ 'x' : 'TPElem',
}};
let {{
@@ -117,6 +120,15 @@ let {{
srtMode = 1
srtEPC = 0
+ def vectorElem(idx, elem):
+ return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)
+
+ def vectorReg(idx, elems = None):
+ return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
+
+ def vectorRegElem(elem, ext = 'sf', zeroing = False):
+ return (elem, ext, zeroing)
+
def floatReg(idx):
return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
@@ -297,86 +309,203 @@ def operands {{
'FpOp2P3': floatReg('(op2 + 3)'),
# Create AArch64 unpacked view of the FP registers
- 'AA64FpOp1P0': floatReg('((op1 * 4) + 0)'),
- 'AA64FpOp1P1': floatReg('((op1 * 4) + 1)'),
- 'AA64FpOp1P2': floatReg('((op1 * 4) + 2)'),
- 'AA64FpOp1P3': floatReg('((op1 * 4) + 3)'),
- 'AA64FpOp2P0': floatReg('((op2 * 4) + 0)'),
- 'AA64FpOp2P1': floatReg('((op2 * 4) + 1)'),
- 'AA64FpOp2P2': floatReg('((op2 * 4) + 2)'),
- 'AA64FpOp2P3': floatReg('((op2 * 4) + 3)'),
- 'AA64FpOp3P0': floatReg('((op3 * 4) + 0)'),
- 'AA64FpOp3P1': floatReg('((op3 * 4) + 1)'),
- 'AA64FpOp3P2': floatReg('((op3 * 4) + 2)'),
- 'AA64FpOp3P3': floatReg('((op3 * 4) + 3)'),
- 'AA64FpDestP0': floatReg('((dest * 4) + 0)'),
- 'AA64FpDestP1': floatReg('((dest * 4) + 1)'),
- 'AA64FpDestP2': floatReg('((dest * 4) + 2)'),
- 'AA64FpDestP3': floatReg('((dest * 4) + 3)'),
- 'AA64FpDest2P0': floatReg('((dest2 * 4) + 0)'),
- 'AA64FpDest2P1': floatReg('((dest2 * 4) + 1)'),
- 'AA64FpDest2P2': floatReg('((dest2 * 4) + 2)'),
- 'AA64FpDest2P3': floatReg('((dest2 * 4) + 3)'),
-
- 'AA64FpOp1P0V0': floatReg('((((op1+0)) * 4) + 0)'),
- 'AA64FpOp1P1V0': floatReg('((((op1+0)) * 4) + 1)'),
- 'AA64FpOp1P2V0': floatReg('((((op1+0)) * 4) + 2)'),
- 'AA64FpOp1P3V0': floatReg('((((op1+0)) * 4) + 3)'),
-
- 'AA64FpOp1P0V1': floatReg('((((op1+1)) * 4) + 0)'),
- 'AA64FpOp1P1V1': floatReg('((((op1+1)) * 4) + 1)'),
- 'AA64FpOp1P2V1': floatReg('((((op1+1)) * 4) + 2)'),
- 'AA64FpOp1P3V1': floatReg('((((op1+1)) * 4) + 3)'),
-
- 'AA64FpOp1P0V2': floatReg('((((op1+2)) * 4) + 0)'),
- 'AA64FpOp1P1V2': floatReg('((((op1+2)) * 4) + 1)'),
- 'AA64FpOp1P2V2': floatReg('((((op1+2)) * 4) + 2)'),
- 'AA64FpOp1P3V2': floatReg('((((op1+2)) * 4) + 3)'),
-
- 'AA64FpOp1P0V3': floatReg('((((op1+3)) * 4) + 0)'),
- 'AA64FpOp1P1V3': floatReg('((((op1+3)) * 4) + 1)'),
- 'AA64FpOp1P2V3': floatReg('((((op1+3)) * 4) + 2)'),
- 'AA64FpOp1P3V3': floatReg('((((op1+3)) * 4) + 3)'),
-
- 'AA64FpOp1P0V0S': floatReg('((((op1+0)%32) * 4) + 0)'),
- 'AA64FpOp1P1V0S': floatReg('((((op1+0)%32) * 4) + 1)'),
- 'AA64FpOp1P2V0S': floatReg('((((op1+0)%32) * 4) + 2)'),
- 'AA64FpOp1P3V0S': floatReg('((((op1+0)%32) * 4) + 3)'),
-
- 'AA64FpOp1P0V1S': floatReg('((((op1+1)%32) * 4) + 0)'),
- 'AA64FpOp1P1V1S': floatReg('((((op1+1)%32) * 4) + 1)'),
- 'AA64FpOp1P2V1S': floatReg('((((op1+1)%32) * 4) + 2)'),
- 'AA64FpOp1P3V1S': floatReg('((((op1+1)%32) * 4) + 3)'),
-
- 'AA64FpOp1P0V2S': floatReg('((((op1+2)%32) * 4) + 0)'),
- 'AA64FpOp1P1V2S': floatReg('((((op1+2)%32) * 4) + 1)'),
- 'AA64FpOp1P2V2S': floatReg('((((op1+2)%32) * 4) + 2)'),
- 'AA64FpOp1P3V2S': floatReg('((((op1+2)%32) * 4) + 3)'),
-
- 'AA64FpOp1P0V3S': floatReg('((((op1+3)%32) * 4) + 0)'),
- 'AA64FpOp1P1V3S': floatReg('((((op1+3)%32) * 4) + 1)'),
- 'AA64FpOp1P2V3S': floatReg('((((op1+3)%32) * 4) + 2)'),
- 'AA64FpOp1P3V3S': floatReg('((((op1+3)%32) * 4) + 3)'),
-
- 'AA64FpDestP0V0': floatReg('((((dest+0)) * 4) + 0)'),
- 'AA64FpDestP1V0': floatReg('((((dest+0)) * 4) + 1)'),
- 'AA64FpDestP2V0': floatReg('((((dest+0)) * 4) + 2)'),
- 'AA64FpDestP3V0': floatReg('((((dest+0)) * 4) + 3)'),
-
- 'AA64FpDestP0V1': floatReg('((((dest+1)) * 4) + 0)'),
- 'AA64FpDestP1V1': floatReg('((((dest+1)) * 4) + 1)'),
- 'AA64FpDestP2V1': floatReg('((((dest+1)) * 4) + 2)'),
- 'AA64FpDestP3V1': floatReg('((((dest+1)) * 4) + 3)'),
-
- 'AA64FpDestP0V0L': floatReg('((((dest+0)%32) * 4) + 0)'),
- 'AA64FpDestP1V0L': floatReg('((((dest+0)%32) * 4) + 1)'),
- 'AA64FpDestP2V0L': floatReg('((((dest+0)%32) * 4) + 2)'),
- 'AA64FpDestP3V0L': floatReg('((((dest+0)%32) * 4) + 3)'),
-
- 'AA64FpDestP0V1L': floatReg('((((dest+1)%32) * 4) + 0)'),
- 'AA64FpDestP1V1L': floatReg('((((dest+1)%32) * 4) + 1)'),
- 'AA64FpDestP2V1L': floatReg('((((dest+1)%32) * 4) + 2)'),
- 'AA64FpDestP3V1L': floatReg('((((dest+1)%32) * 4) + 3)'),
+ # Name ::= 'AA64Vec' OpSpec [LaneSpec]
+ # OpSpec ::= IOSpec [Index] [Plus]
+ # IOSpec ::= 'S' | 'D'
+ # Index ::= '0' | ... | '9'
+ # Plus ::= [PlusAmount] ['l']
+ # PlusAmount ::= 'p' [PlusAmount]
+ # LaneSpec ::= 'L' Index
+ #
+ # All the constituents are hierarchically defined as part of the Vector
+ # Register they belong to
+
+ 'AA64FpOp1': vectorReg('op1',
+ {
+ 'AA64FpOp1P0': vectorRegElem('0'),
+ 'AA64FpOp1P1': vectorRegElem('1'),
+ 'AA64FpOp1P2': vectorRegElem('2'),
+ 'AA64FpOp1P3': vectorRegElem('3'),
+ 'AA64FpOp1S': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpOp1D': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpOp1Q': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpOp2': vectorReg('op2',
+ {
+ 'AA64FpOp2P0': vectorRegElem('0'),
+ 'AA64FpOp2P1': vectorRegElem('1'),
+ 'AA64FpOp2P2': vectorRegElem('2'),
+ 'AA64FpOp2P3': vectorRegElem('3'),
+ 'AA64FpOp2S': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpOp2D': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpOp2Q': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpOp3': vectorReg('op3',
+ {
+ 'AA64FpOp3P0': vectorRegElem('0'),
+ 'AA64FpOp3P1': vectorRegElem('1'),
+ 'AA64FpOp3P2': vectorRegElem('2'),
+ 'AA64FpOp3P3': vectorRegElem('3'),
+ 'AA64FpOp3S': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpOp3D': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpOp3Q': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpDest': vectorReg('dest',
+ {
+ 'AA64FpDestP0': vectorRegElem('0'),
+ 'AA64FpDestP1': vectorRegElem('1'),
+ 'AA64FpDestP2': vectorRegElem('2'),
+ 'AA64FpDestP3': vectorRegElem('3'),
+ 'AA64FpDestS': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpDestD': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpDestQ': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpDest2': vectorReg('dest2',
+ {
+ 'AA64FpDest2P0': vectorRegElem('0'),
+ 'AA64FpDest2P1': vectorRegElem('1'),
+ 'AA64FpDest2P2': vectorRegElem('2'),
+ 'AA64FpDest2P3': vectorRegElem('3'),
+ 'AA64FpDest2S': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpDest2D': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpDest2Q': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpOp1V0': vectorReg('op1',
+ {
+ 'AA64FpOp1P0V0': vectorRegElem('0'),
+ 'AA64FpOp1P1V0': vectorRegElem('1'),
+ 'AA64FpOp1P2V0': vectorRegElem('2'),
+ 'AA64FpOp1P3V0': vectorRegElem('3'),
+ 'AA64FpOp1SV0': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpOp1DV0': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpOp1QV0': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpOp1V1': vectorReg('op1+1',
+ {
+ 'AA64FpOp1P0V1': vectorRegElem('0'),
+ 'AA64FpOp1P1V1': vectorRegElem('1'),
+ 'AA64FpOp1P2V1': vectorRegElem('2'),
+ 'AA64FpOp1P3V1': vectorRegElem('3'),
+ 'AA64FpOp1SV1': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpOp1DV1': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpOp1QV1': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpOp1V2': vectorReg('op1+2',
+ {
+ 'AA64FpOp1P0V2': vectorRegElem('0'),
+ 'AA64FpOp1P1V2': vectorRegElem('1'),
+ 'AA64FpOp1P2V2': vectorRegElem('2'),
+ 'AA64FpOp1P3V2': vectorRegElem('3'),
+ 'AA64FpOp1SV2': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpOp1DV2': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpOp1QV2': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpOp1V3': vectorReg('op1+3',
+ {
+ 'AA64FpOp1P0V3': vectorRegElem('0'),
+ 'AA64FpOp1P1V3': vectorRegElem('1'),
+ 'AA64FpOp1P2V3': vectorRegElem('2'),
+ 'AA64FpOp1P3V3': vectorRegElem('3'),
+ 'AA64FpOp1SV3': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpOp1DV3': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpOp1QV3': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpOp1V0S': vectorReg('(op1+0)%32',
+ {
+ 'AA64FpOp1P0V0S': vectorRegElem('0'),
+ 'AA64FpOp1P1V0S': vectorRegElem('1'),
+ 'AA64FpOp1P2V0S': vectorRegElem('2'),
+ 'AA64FpOp1P3V0S': vectorRegElem('3'),
+ 'AA64FpOp1SV0S': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpOp1DV0S': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpOp1QV0S': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpOp1V1S': vectorReg('(op1+1)%32',
+ {
+ 'AA64FpOp1P0V1S': vectorRegElem('0'),
+ 'AA64FpOp1P1V1S': vectorRegElem('1'),
+ 'AA64FpOp1P2V1S': vectorRegElem('2'),
+ 'AA64FpOp1P3V1S': vectorRegElem('3'),
+ 'AA64FpOp1SV1S': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpOp1DV1S': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpOp1QV1S': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpOp1V2S': vectorReg('(op1+2)%32',
+ {
+ 'AA64FpOp1P0V2S': vectorRegElem('0'),
+ 'AA64FpOp1P1V2S': vectorRegElem('1'),
+ 'AA64FpOp1P2V2S': vectorRegElem('2'),
+ 'AA64FpOp1P3V2S': vectorRegElem('3'),
+ 'AA64FpOp1SV2S': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpOp1DV2S': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpOp1QV2S': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpOp1V3S': vectorReg('(op1+3)%32',
+ {
+ 'AA64FpOp1P0V3S': vectorRegElem('0'),
+ 'AA64FpOp1P1V3S': vectorRegElem('1'),
+ 'AA64FpOp1P2V3S': vectorRegElem('2'),
+ 'AA64FpOp1P3V3S': vectorRegElem('3'),
+ 'AA64FpOp1SV3S': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpOp1DV3S': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpOp1QV3S': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpDestV0': vectorReg('(dest+0)',
+ {
+ 'AA64FpDestP0V0': vectorRegElem('0'),
+ 'AA64FpDestP1V0': vectorRegElem('1'),
+ 'AA64FpDestP2V0': vectorRegElem('2'),
+ 'AA64FpDestP3V0': vectorRegElem('3'),
+ 'AA64FpDestSV0': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpDestDV0': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpDestQV0': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpDestV1': vectorReg('(dest+1)',
+ {
+ 'AA64FpDestP0V1': vectorRegElem('0'),
+ 'AA64FpDestP1V1': vectorRegElem('1'),
+ 'AA64FpDestP2V1': vectorRegElem('2'),
+ 'AA64FpDestP3V1': vectorRegElem('3'),
+ 'AA64FpDestSV1': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpDestDV1': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpDestQV1': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpDestV0L': vectorReg('(dest+0)%32',
+ {
+ 'AA64FpDestP0V0L': vectorRegElem('0'),
+ 'AA64FpDestP1V0L': vectorRegElem('1'),
+ 'AA64FpDestP2V0L': vectorRegElem('2'),
+ 'AA64FpDestP3V0L': vectorRegElem('3'),
+ 'AA64FpDestSV0L': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpDestDV0L': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpDestQV0L': vectorRegElem('0', 'tud', zeroing = True)
+ }),
+
+ 'AA64FpDestV1L': vectorReg('(dest+1)%32',
+ {
+ 'AA64FpDestP0V1L': vectorRegElem('0'),
+ 'AA64FpDestP1V1L': vectorRegElem('1'),
+ 'AA64FpDestP2V1L': vectorRegElem('2'),
+ 'AA64FpDestP3V1L': vectorRegElem('3'),
+ 'AA64FpDestSV1L': vectorRegElem('0', 'sf', zeroing = True),
+ 'AA64FpDestDV1L': vectorRegElem('0', 'df', zeroing = True),
+ 'AA64FpDestQV1L': vectorRegElem('0', 'tud', zeroing = True)
+ }),
#Abstracted control reg operands
'MiscDest': cntrlReg('dest'),
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 51f598f50..a0942d151 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010, 2012, 2014 ARM Limited
+// Copyright (c) 2010, 2012, 2014, 2016 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -1150,7 +1150,7 @@ def template LoadRegConstructor {{
#if %(use_uops)d
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
- if (_dest == INTREG_PC && !isFloating()) {
+ if (_dest == INTREG_PC && !isFloating() && !isVector()) {
IntRegIndex wbIndexReg = index;
uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
_shiftAmt, _shiftType, _index);
@@ -1187,7 +1187,7 @@ def template LoadRegConstructor {{
}
#else
- if (_dest == INTREG_PC && !isFloating()) {
+ if (_dest == INTREG_PC && !isFloating() && !isVector()) {
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (conditional)
@@ -1216,7 +1216,7 @@ def template LoadImmConstructor {{
#if %(use_uops)d
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
- if (_dest == INTREG_PC && !isFloating()) {
+ if (_dest == INTREG_PC && !isFloating() && !isVector()) {
uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
_imm);
uops[0]->setDelayedCommit();
@@ -1250,7 +1250,7 @@ def template LoadImmConstructor {{
uops[1]->setLastMicroop();
}
#else
- if (_dest == INTREG_PC && !isFloating()) {
+ if (_dest == INTREG_PC && !isFloating() && !isVector()) {
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (conditional)
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 752ab8d1e..7b372bdee 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010 ARM Limited
+// Copyright (c) 2010, 2016 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -77,7 +77,7 @@ def template DataImmConstructor {{
}
}
- if (%(is_branch)s && !isFloating()){
+ if (%(is_branch)s && !isFloating() && !isVector()){
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (condCode == COND_AL || condCode == COND_UC)
@@ -117,7 +117,7 @@ def template DataRegConstructor {{
}
}
- if (%(is_branch)s && !isFloating()){
+ if (%(is_branch)s && !isFloating() && !isVector()){
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (condCode == COND_AL || condCode == COND_UC)
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 15:05:18 +0000