diff options
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/SConscript | 1 | ||||
| -rw-r--r-- | src/arch/arm/isa.cc | 79 | ||||
| -rw-r--r-- | src/arch/arm/isa.hh | 79 | ||||
| -rw-r--r-- | src/arch/arm/regfile/misc_regfile.hh | 1 | ||||
| -rw-r--r-- | src/arch/arm/regfile/regfile.cc | 11 | ||||
| -rw-r--r-- | src/arch/arm/regfile/regfile.hh | 37 |
6 files changed, 160 insertions, 48 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 60a5ca3b0..a88a911f7 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -39,6 +39,7 @@ if env['TARGET_ISA'] == 'arm': Source('insts/mem.cc') Source('insts/pred_inst.cc') Source('insts/static_inst.cc') + Source('isa.cc') Source('pagetable.cc') Source('regfile/regfile.cc') Source('tlb.cc') diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc new file mode 100644 index 000000000..944f19c0b --- /dev/null +++ b/src/arch/arm/isa.cc @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2009 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#include "arch/arm/isa.hh" +#include "cpu/thread_context.hh" + +namespace ArmISA +{ + +void +ISA::clear() +{ + miscRegFile.clear(); +} + +MiscReg +ISA::readMiscRegNoEffect(int miscReg) +{ + return miscRegFile.readRegNoEffect(miscReg); +} + +MiscReg +ISA::readMiscReg(int miscReg, ThreadContext *tc) +{ + return miscRegFile.readReg(miscReg, tc); +} + +void +ISA::setMiscRegNoEffect(int miscReg, const MiscReg val) +{ + miscRegFile.setRegNoEffect(miscReg, val); +} + +void +ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc) +{ + miscRegFile.setReg(miscReg, val, tc); +} + +void +ISA::serialize(std::ostream &os) +{ + //miscRegFile.serialize(os); +} + +void +ISA::unserialize(Checkpoint *cp, const std::string §ion) +{ + //miscRegFile.unserialize(cp, section); +} + +} diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh new file mode 100644 index 000000000..cb207bf13 --- /dev/null +++ b/src/arch/arm/isa.hh @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2009 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Gabe Black + */ + +#ifndef __ARCH_ARM_ISA_HH__ +#define __ARCH_MRM_ISA_HH__ + +#include "arch/arm/regfile/misc_regfile.hh" +#include "arch/arm/types.hh" + +class Checkpoint; +class EventManager; + +namespace ArmISA +{ + class ISA + { + protected: + MiscRegFile miscRegFile; + + public: + void clear(); + + MiscReg readMiscRegNoEffect(int miscReg); + MiscReg readMiscReg(int miscReg, ThreadContext *tc); + + void setMiscRegNoEffect(int miscReg, const MiscReg val); + void setMiscReg(int miscReg, const MiscReg val, + ThreadContext *tc); + + int + flattenIntIndex(int reg) + { + return reg; + } + + int + flattenFloatIndex(int reg) + { + return reg; + } + + void serialize(std::ostream &os); + void unserialize(Checkpoint *cp, const std::string §ion); + + ISA() + { + clear(); + } + }; +} + +#endif diff --git a/src/arch/arm/regfile/misc_regfile.hh b/src/arch/arm/regfile/misc_regfile.hh index f7e5fbd98..eda0e8f05 100644 --- a/src/arch/arm/regfile/misc_regfile.hh +++ b/src/arch/arm/regfile/misc_regfile.hh @@ -31,6 +31,7 @@ #ifndef __ARCH_ARM_REGFILE_MISC_REGFILE_HH__ #define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__ +#include "arch/arm/isa_traits.hh" #include "arch/arm/types.hh" #include "sim/faults.hh" diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc index a4d6e9a4a..9821630e3 100644 --- a/src/arch/arm/regfile/regfile.cc +++ b/src/arch/arm/regfile/regfile.cc @@ -59,11 +59,6 @@ RegFile::serialize(EventManager *em, ostream &os) { intRegFile.serialize(os); //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs); - //SERIALZE_ARRAY(miscRegFile); - //SERIALIZE_SCALAR(miscRegs.fpcr); - //SERIALIZE_SCALAR(miscRegs.lock_flag); - //SERIALIZE_SCALAR(miscRegs.lock_addr); - //SERIALIZE_SCALAR(pc); SERIALIZE_SCALAR(npc); SERIALIZE_SCALAR(nnpc); } @@ -73,14 +68,8 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) { intRegFile.unserialize(cp, section); //UNSERIALIZE_ARRAY(floatRegFile); - //UNSERIALZE_ARRAY(miscRegFile); - //UNSERIALIZE_SCALAR(miscRegs.fpcr); - //UNSERIALIZE_SCALAR(miscRegs.lock_flag); - //UNSERIALIZE_SCALAR(miscRegs.lock_addr); - //UNSERIALIZE_SCALAR(pc); UNSERIALIZE_SCALAR(npc); UNSERIALIZE_SCALAR(nnpc); - } } // namespace ArmISA diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh index 5a812fecf..c432c0c28 100644 --- a/src/arch/arm/regfile/regfile.hh +++ b/src/arch/arm/regfile/regfile.hh @@ -48,7 +48,6 @@ namespace ArmISA protected: IntRegFile intRegFile; // (signed) integer register file FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegFile; // control register file public: @@ -56,28 +55,6 @@ namespace ArmISA { intRegFile.clear(); floatRegFile.clear(); - miscRegFile.clear(); - } - - MiscReg readMiscRegNoEffect(int miscReg) - { - return miscRegFile.readRegNoEffect(miscReg); - } - - MiscReg readMiscReg(int miscReg, ThreadContext *tc) - { - return miscRegFile.readReg(miscReg, tc); - } - - void setMiscRegNoEffect(int miscReg, const MiscReg &val) - { - miscRegFile.setRegNoEffect(miscReg, val); - } - - void setMiscReg(int miscReg, const MiscReg &val, - ThreadContext * tc) - { - miscRegFile.setReg(miscReg, val, tc); } FloatRegVal readFloatReg(int floatReg) @@ -171,22 +148,8 @@ namespace ArmISA void serialize(EventManager *em, std::ostream &os); void unserialize(EventManager *em, Checkpoint *cp, const std::string §ion); - - void changeContext(RegContextParam param, RegContextVal val) - { - } }; - static inline int flattenIntIndex(ThreadContext * tc, int reg) - { - return reg; - } - - static inline int flattenFloatIndex(ThreadContext * tc, int reg) - { - return reg; - } - void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); |