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-rw-r--r--src/arch/arm/isa/decoder/arm.isa26
-rw-r--r--src/arch/arm/isa/formats/fp.isa103
2 files changed, 0 insertions, 129 deletions
diff --git a/src/arch/arm/isa/decoder/arm.isa b/src/arch/arm/isa/decoder/arm.isa
index 1e0d61b3f..49f70e5e4 100644
--- a/src/arch/arm/isa/decoder/arm.isa
+++ b/src/arch/arm/isa/decoder/arm.isa
@@ -148,32 +148,6 @@ format DataOp {
0xa, 0xb: VfpData::vfpData();
} // CPNUM
1: decode CPNUM { // 27-24=1110,4 ==1
- 1: decode OPCODE_15_12 {
- format FloatOp {
- 0xf: decode OPCODE_23_21 {
- format FloatCmp {
- 0x4: cmf({{ Fn.df }}, {{ Fm.df }});
- 0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
- 0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
- 0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
- }
- }
- default: decode OPCODE_23_20 {
- 0x0: decode OPCODE_7 {
- 0: flts({{ Fn.sf = (float) Rd.sw; }});
- 1: fltd({{ Fn.df = (double) Rd.sw; }});
- }
- 0x1: decode OPCODE_7 {
- 0: fixs({{ Rd = (uint32_t) Fm.sf; }});
- 1: fixd({{ Rd = (uint32_t) Fm.df; }});
- }
- 0x2: wfs({{ Fpsr = Rd; }});
- 0x3: rfs({{ Rd = Fpsr; }});
- 0x4: FailUnimpl::wfc();
- 0x5: FailUnimpl::rfc();
- }
- } // format FloatOp
- }
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
0xf: McrMrc15::mcrMrc15();
} // CPNUM (OP4 == 1)
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 03e574648..55668e5f6 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -45,109 +45,6 @@
// Floating Point operate instructions
//
-def template FPAExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
- {
- Fault fault = NoFault;
-
- %(fp_enable_check)s;
-
- %(op_decl)s;
- %(op_rd)s;
-
- if (%(predicate_test)s) {
- %(code)s;
- if (fault == NoFault) {
- %(op_wb)s;
- }
- }
-
- return fault;
- }
-}};
-
-def template FloatDoubleDecode {{
- {
- ArmStaticInst *i = NULL;
- switch (OPCODE_19 << 1 | OPCODE_7)
- {
- case 0:
- i = (ArmStaticInst *)new %(class_name)sS(machInst);
- break;
- case 1:
- i = (ArmStaticInst *)new %(class_name)sD(machInst);
- break;
- case 2:
- case 3:
- default:
- panic("Cannot decode float/double nature of the instruction");
- }
- return i;
- }
-}};
-
-// Primary format for float point operate instructions:
-def format FloatOp(code, *flags) {{
- orig_code = code
-
- cblk = code
- iop = InstObjParams(name, Name, 'PredOp',
- {"code": cblk,
- "predicate_test": predicateTest},
- flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- exec_output = FPAExecute.subst(iop)
-
- sng_cblk = code
- sng_iop = InstObjParams(name, Name+'S', 'PredOp',
- {"code": sng_cblk,
- "predicate_test": predicateTest},
- flags)
- header_output += BasicDeclare.subst(sng_iop)
- decoder_output += BasicConstructor.subst(sng_iop)
- exec_output += FPAExecute.subst(sng_iop)
-
- dbl_code = re.sub(r'\.sf', '.df', orig_code)
-
- dbl_cblk = dbl_code
- dbl_iop = InstObjParams(name, Name+'D', 'PredOp',
- {"code": dbl_cblk,
- "predicate_test": predicateTest},
- flags)
- header_output += BasicDeclare.subst(dbl_iop)
- decoder_output += BasicConstructor.subst(dbl_iop)
- exec_output += FPAExecute.subst(dbl_iop)
-
- decode_block = FloatDoubleDecode.subst(iop)
-}};
-
-let {{
- calcFPCcCode = '''
- uint16_t _in, _iz, _ic, _iv;
-
- _in = %(fReg1)s < %(fReg2)s;
- _iz = %(fReg1)s == %(fReg2)s;
- _ic = %(fReg1)s >= %(fReg2)s;
- _iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1;
-
- CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
- (CondCodes & 0x0FFFFFFF);
- '''
-}};
-
-def format FloatCmp(fReg1, fReg2, *flags) {{
- code = calcFPCcCode % vars()
- iop = InstObjParams(name, Name, 'PredOp',
- {"code": code,
- "predicate_test": predicateTest},
- flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = FPAExecute.subst(iop)
-}};
-
let {{
header_output = '''
StaticInstPtr