diff options
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa.cc | 4 | ||||
| -rw-r--r-- | src/arch/arm/tlb.cc | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index d3286a6b0..0b753087e 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1520,7 +1520,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) // can't be an atomic translation because that causes problems // with unexpected atomic snoop requests. warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); - Request req(0, val, 1, flags, Request::funcMasterId, + Request req(0, val, 0, flags, Request::funcMasterId, tc->pcState().pc(), tc->contextId()); fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); @@ -1765,7 +1765,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) // can't be an atomic translation because that causes problems // with unexpected atomic snoop requests. warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); - req->setVirt(0, val, 1, flags, Request::funcMasterId, + req->setVirt(0, val, 0, flags, Request::funcMasterId, tc->pcState().pc()); req->setContext(tc->contextId()); fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index f4d51546c..a499900e0 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1423,7 +1423,7 @@ TLB::setTestInterface(SimObject *_ti) Fault TLB::testTranslation(RequestPtr req, Mode mode, TlbEntry::DomainType domain) { - if (!test) { + if (!test || !req->hasSize() || req->getSize() == 0) { return NoFault; } else { return test->translationCheck(req, isPriv, mode, domain); |