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-rw-r--r--src/arch/arm/linux/process.cc12
-rw-r--r--src/arch/arm/linux/system.cc40
-rw-r--r--src/arch/arm/process.cc1
-rw-r--r--src/arch/arm/stacktrace.cc6
-rw-r--r--src/arch/arm/system.cc34
-rw-r--r--src/arch/arm/system.hh5
-rw-r--r--src/arch/arm/utility.cc4
-rw-r--r--src/arch/arm/vtophys.cc4
8 files changed, 58 insertions, 48 deletions
diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc
index c65962d00..1074b0362 100644
--- a/src/arch/arm/linux/process.cc
+++ b/src/arch/arm/linux/process.cc
@@ -70,7 +70,7 @@ unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
strcpy(name->machine, "armv7l");
- name.copyOut(tc->getMemPort());
+ name.copyOut(tc->getMemProxy());
return 0;
}
@@ -452,7 +452,7 @@ setTLSFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
int index = 0;
uint32_t tlsPtr = process->getSyscallArg(tc, index);
- tc->getMemPort()->writeBlob(ArmLinuxProcess::commPage + 0x0ff0,
+ tc->getMemProxy()->writeBlob(ArmLinuxProcess::commPage + 0x0ff0,
(uint8_t *)&tlsPtr, sizeof(tlsPtr));
tc->setMiscReg(MISCREG_TPIDRURO,tlsPtr);
return 0;
@@ -512,7 +512,7 @@ ArmLinuxProcess::initState()
// Fill this page with swi -1 so we'll no if we land in it somewhere.
for (Addr addr = 0; addr < PageBytes; addr += sizeof(swiNeg1)) {
- tc->getMemPort()->writeBlob(commPage + addr,
+ tc->getMemProxy()->writeBlob(commPage + addr,
swiNeg1, sizeof(swiNeg1));
}
@@ -521,7 +521,7 @@ ArmLinuxProcess::initState()
0x5f, 0xf0, 0x7f, 0xf5, // dmb
0x0e, 0xf0, 0xa0, 0xe1 // return
};
- tc->getMemPort()->writeBlob(commPage + 0x0fa0, memory_barrier,
+ tc->getMemProxy()->writeBlob(commPage + 0x0fa0, memory_barrier,
sizeof(memory_barrier));
uint8_t cmpxchg[] =
@@ -535,7 +535,7 @@ ArmLinuxProcess::initState()
0x5f, 0xf0, 0x7f, 0xf5, // dmb
0x0e, 0xf0, 0xa0, 0xe1 // return
};
- tc->getMemPort()->writeBlob(commPage + 0x0fc0, cmpxchg, sizeof(cmpxchg));
+ tc->getMemProxy()->writeBlob(commPage + 0x0fc0, cmpxchg, sizeof(cmpxchg));
uint8_t get_tls[] =
{
@@ -543,7 +543,7 @@ ArmLinuxProcess::initState()
0x70, 0x0f, 0x1d, 0xee, // mrc p15, 0, r0, c13, c0, 3
0x0e, 0xf0, 0xa0, 0xe1 // return
};
- tc->getMemPort()->writeBlob(commPage + 0x0fe0, get_tls, sizeof(get_tls));
+ tc->getMemProxy()->writeBlob(commPage + 0x0fe0, get_tls, sizeof(get_tls));
}
ArmISA::IntReg
diff --git a/src/arch/arm/linux/system.cc b/src/arch/arm/linux/system.cc
index 66f4f26af..a764edaca 100644
--- a/src/arch/arm/linux/system.cc
+++ b/src/arch/arm/linux/system.cc
@@ -49,6 +49,7 @@
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "kern/linux/events.hh"
+#include "mem/fs_translating_port_proxy.hh"
#include "mem/physical.hh"
using namespace ArmISA;
@@ -57,6 +58,27 @@ using namespace Linux;
LinuxArmSystem::LinuxArmSystem(Params *p)
: ArmSystem(p)
{
+}
+
+bool
+LinuxArmSystem::adderBootUncacheable(Addr a)
+{
+ Addr block = a & ~ULL(0x7F);
+ if (block == secDataPtrAddr || block == secDataAddr ||
+ block == penReleaseAddr)
+ return true;
+ return false;
+}
+
+void
+LinuxArmSystem::initState()
+{
+ // Moved from the constructor to here since it relies on the
+ // address map being resolved in the interconnect
+
+ // Call the initialisation of the super class
+ ArmSystem::initState();
+
// Load symbols at physical address, we might not want
// to do this perminately, for but early bootup work
// it is helpfulp.
@@ -92,7 +114,7 @@ LinuxArmSystem::LinuxArmSystem(Params *p)
DPRINTF(Loader, "Boot atags was %d bytes in total\n", size << 2);
DDUMP(Loader, boot_data, size << 2);
- functionalPort->writeBlob(ParamsList, boot_data, size << 2);
+ physProxy->writeBlob(ParamsList, boot_data, size << 2);
#ifndef NDEBUG
kernelPanicEvent = addKernelFuncEvent<BreakPCEvent>("panic");
@@ -128,22 +150,6 @@ LinuxArmSystem::LinuxArmSystem(Params *p)
secDataPtrAddr &= ~ULL(0x7F);
secDataAddr &= ~ULL(0x7F);
penReleaseAddr &= ~ULL(0x7F);
-}
-
-bool
-LinuxArmSystem::adderBootUncacheable(Addr a)
-{
- Addr block = a & ~ULL(0x7F);
- if (block == secDataPtrAddr || block == secDataAddr ||
- block == penReleaseAddr)
- return true;
- return false;
-}
-
-void
-LinuxArmSystem::initState()
-{
- ArmSystem::initState();
for (int i = 0; i < threadContexts.size(); i++) {
threadContexts[i]->setIntReg(0, 0);
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index aa5d7dfce..c149f5409 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -50,7 +50,6 @@
#include "cpu/thread_context.hh"
#include "debug/Stack.hh"
#include "mem/page_table.hh"
-#include "mem/translating_port.hh"
#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/system.hh"
diff --git a/src/arch/arm/stacktrace.cc b/src/arch/arm/stacktrace.cc
index 31376cdae..69d0f354c 100644
--- a/src/arch/arm/stacktrace.cc
+++ b/src/arch/arm/stacktrace.cc
@@ -37,7 +37,7 @@
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#include "mem/vport.hh"
+#include "mem/fs_translating_port_proxy.hh"
#include "sim/system.hh"
using namespace std;
@@ -48,9 +48,9 @@ namespace ArmISA
{
Addr addr = 0;
- VirtualPort *vp;
+ FSTranslatingPortProxy* vp;
- vp = tc->getVirtPort();
+ vp = tc->getVirtProxy();
if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
panic("thread info not compiled into kernel\n");
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 4d4dff4d9..ca5bfc471 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -47,6 +47,7 @@
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
#include "mem/physical.hh"
+#include "mem/fs_translating_port_proxy.hh"
using namespace std;
using namespace Linux;
@@ -55,6 +56,18 @@ ArmSystem::ArmSystem(Params *p)
: System(p), bootldr(NULL)
{
debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk");
+}
+
+void
+ArmSystem::initState()
+{
+ // Moved from the constructor to here since it relies on the
+ // address map being resolved in the interconnect
+
+ // Call the initialisation of the super class
+ System::initState();
+
+ const Params* p = params();
if ((p->boot_loader == "") != (p->boot_loader_mem == NULL))
fatal("If boot_loader is specifed, memory to load it must be also.\n");
@@ -65,29 +78,18 @@ ArmSystem::ArmSystem(Params *p)
if (!bootldr)
fatal("Could not read bootloader: %s\n", p->boot_loader);
- Port *mem_port;
- FunctionalPort fp(name() + "-fport");
- mem_port = p->boot_loader_mem->getPort("functional");
- fp.setPeer(mem_port);
- mem_port->setPeer(&fp);
-
- bootldr->loadSections(&fp);
+ bootldr->loadSections(physProxy);
bootldr->loadGlobalSymbols(debugSymbolTable);
uint8_t jump_to_bl[] =
{
0x07, 0xf0, 0xa0, 0xe1 // branch to r7
};
- functionalPort->writeBlob(0x0, jump_to_bl, sizeof(jump_to_bl));
+ physProxy->writeBlob(0x0, jump_to_bl, sizeof(jump_to_bl));
inform("Using bootloader at address %#x\n", bootldr->entryPoint());
}
-}
-void
-ArmSystem::initState()
-{
- System::initState();
if (bootldr) {
// Put the address of the boot loader into r7 so we know
// where to branch to after the reset fault
@@ -98,16 +100,16 @@ ArmSystem::initState()
threadContexts[i]->setIntReg(5, params()->flags_addr);
threadContexts[i]->setIntReg(7, bootldr->entryPoint());
}
- if (!params()->gic_cpu_addr || !params()->flags_addr)
+ if (!p->gic_cpu_addr || !p->flags_addr)
fatal("gic_cpu_addr && flags_addr must be set with bootloader\n");
} else {
// Set the initial PC to be at start of the kernel code
threadContexts[0]->pcState(kernelEntry & loadAddrMask);
}
for (int i = 0; i < threadContexts.size(); i++) {
- if (params()->midr_regval) {
+ if (p->midr_regval) {
threadContexts[i]->setMiscReg(ArmISA::MISCREG_MIDR,
- params()->midr_regval);
+ p->midr_regval);
}
}
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index 32b48a85b..7cf36fd6c 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -76,7 +76,10 @@ class ArmSystem : public System
ArmSystem(Params *p);
~ArmSystem();
- void initState();
+ /**
+ * Initialise the system
+ */
+ virtual void initState();
/** Check if an address should be uncacheable until all caches are enabled.
* This exits because coherence on some addresses at boot is maintained via
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index bbba38d2b..98195ab04 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -45,7 +45,7 @@
#if FULL_SYSTEM
#include "arch/arm/vtophys.hh"
-#include "mem/vport.hh"
+#include "mem/fs_translating_port_proxy.hh"
#endif
#include "arch/arm/tlb.hh"
@@ -89,7 +89,7 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
}
} else {
Addr sp = tc->readIntReg(StackPointerReg);
- VirtualPort *vp = tc->getVirtPort();
+ FSTranslatingPortProxy* vp = tc->getVirtProxy();
uint64_t arg;
if (size == sizeof(uint64_t)) {
// If the argument is even it must be aligned
diff --git a/src/arch/arm/vtophys.cc b/src/arch/arm/vtophys.cc
index 1691a387c..45e6f1849 100644
--- a/src/arch/arm/vtophys.cc
+++ b/src/arch/arm/vtophys.cc
@@ -51,7 +51,7 @@
#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
-#include "mem/vport.hh"
+#include "mem/fs_translating_port_proxy.hh"
using namespace std;
using namespace ArmISA;
@@ -101,7 +101,7 @@ ArmISA::vtophys(ThreadContext *tc, Addr addr)
N = 0;
}
- FunctionalPort *port = tc->getPhysPort();
+ PortProxy* port = tc->getPhysProxy();
Addr l1desc_addr = mbits(ttbr, 31, 14-N) | (bits(addr,31-N,20) << 2);
TableWalker::L1Descriptor l1desc;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 06:35:21 +0000