diff options
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/faults.hh | 12 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/data64.isa | 9 | ||||
| -rw-r--r-- | src/arch/arm/isa/templates/vfp.isa | 8 |
3 files changed, 17 insertions, 12 deletions
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index a5720f115..8a6f07dde 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -257,9 +257,9 @@ class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> { protected: bool unknown; - const char *mnemonic; bool disabled; ExceptionClass overrideEc; + const char *mnemonic; public: UndefinedInstruction(ExtMachInst _machInst, @@ -267,12 +267,14 @@ class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> const char *_mnemonic = NULL, bool _disabled = false) : ArmFaultVals<UndefinedInstruction>(_machInst), - unknown(_unknown), mnemonic(_mnemonic), disabled(_disabled), - overrideEc(EC_INVALID) + unknown(_unknown), disabled(_disabled), + overrideEc(EC_INVALID), mnemonic(_mnemonic) {} - UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc) : + UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, + ExceptionClass _overrideEc, const char *_mnemonic = NULL) : ArmFaultVals<UndefinedInstruction>(_machInst, _iss), - overrideEc(_overrideEc) + unknown(false), disabled(true), overrideEc(_overrideEc), + mnemonic(_mnemonic) {} void invoke(ThreadContext *tc, diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa index 77d7541ca..8ec446d16 100644 --- a/src/arch/arm/isa/insts/data64.isa +++ b/src/arch/arm/isa/insts/data64.isa @@ -294,7 +294,8 @@ let {{ flat_idx == MISCREG_DC_CVAC_Xt || flat_idx == MISCREG_DC_CIVAC_Xt ) - return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64); + return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64, + mnemonic); return new UndefinedInstruction(machInst, false, mnemonic); } @@ -396,7 +397,8 @@ let {{ if (!canWriteAArch64SysReg( (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest), Scr64, Cpsr, xc->tcBase())) { - return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64); + return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64, + mnemonic); } CPSR cpsr = Cpsr; cpsr.daif = cpsr.daif | imm; @@ -407,7 +409,8 @@ let {{ if (!canWriteAArch64SysReg( (MiscRegIndex) xc->tcBase()->flattenMiscIndex(dest), Scr64, Cpsr, xc->tcBase())) { - return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64); + return new UndefinedInstruction(machInst, 0, EC_TRAPPED_MSR_MRS_64, + mnemonic); } CPSR cpsr = Cpsr; cpsr.daif = cpsr.daif & ~imm; diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa index fbd7275d5..45be8a5f3 100644 --- a/src/arch/arm/isa/templates/vfp.isa +++ b/src/arch/arm/isa/templates/vfp.isa @@ -49,7 +49,7 @@ let {{ CPSR cpsrEnCheck = Cpsr; if (cpsrEnCheck.mode == MODE_HYP) { return new UndefinedInstruction(machInst, issEnCheck, - EC_TRAPPED_HCPTR); + EC_TRAPPED_HCPTR, mnemonic); } else { if (!inSecureState(Scr, Cpsr)) { return new HypervisorTrap(machInst, issEnCheck, @@ -96,7 +96,7 @@ let {{ CPSR cpsrEnCheck = Cpsr; if (cpsrEnCheck.mode == MODE_HYP) { return new UndefinedInstruction(machInst, issEnCheck, - EC_TRAPPED_HCPTR); + EC_TRAPPED_HCPTR, mnemonic); } else { if (!inSecureState(Scr, Cpsr)) { return new HypervisorTrap(machInst, issEnCheck, @@ -122,7 +122,7 @@ let {{ CPSR cpsrEnCheck = Cpsr; if (cpsrEnCheck.mode == MODE_HYP) { return new UndefinedInstruction(machInst, issEnCheck, - EC_TRAPPED_HCPTR); + EC_TRAPPED_HCPTR, mnemonic); } else { if (!inSecureState(Scr, Cpsr)) { return new HypervisorTrap(machInst, issEnCheck, @@ -142,7 +142,7 @@ let {{ CPSR cpsrEnCheck = Cpsr; if (cpsrEnCheck.mode == MODE_HYP) { return new UndefinedInstruction(machInst, issEnCheck, - EC_TRAPPED_HCPTR); + EC_TRAPPED_HCPTR, mnemonic); } else { if (!inSecureState(Scr, Cpsr)) { return new HypervisorTrap(machInst, issEnCheck, |