summaryrefslogtreecommitdiff
path: root/src/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/faults.cc18
-rw-r--r--src/arch/arm/faults.hh18
-rw-r--r--src/arch/arm/isa.cc1
-rw-r--r--src/arch/arm/isa/includes.isa1
-rw-r--r--src/arch/arm/nativetrace.cc1
-rw-r--r--src/arch/arm/process.cc1
-rw-r--r--src/arch/arm/table_walker.hh2
-rw-r--r--src/arch/arm/tlb.hh2
-rw-r--r--src/arch/arm/utility.hh1
9 files changed, 29 insertions, 16 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 2a6b7c359..a5ecdad25 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -94,7 +94,7 @@ ArmFault::getVector(ThreadContext *tc)
#if FULL_SYSTEM
void
-ArmFault::invoke(ThreadContext *tc)
+ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
// ARM ARM B1.6.3
FaultBase::invoke(tc);
@@ -150,7 +150,7 @@ ArmFault::invoke(ThreadContext *tc)
}
void
-Reset::invoke(ThreadContext *tc)
+Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
{
tc->getCpuPtr()->clearInterrupts();
tc->clearArchRegs();
@@ -160,7 +160,7 @@ Reset::invoke(ThreadContext *tc)
#else
void
-UndefinedInstruction::invoke(ThreadContext *tc)
+UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
{
// If the mnemonic isn't defined this has to be an unknown instruction.
assert(unknown || mnemonic != NULL);
@@ -177,7 +177,7 @@ UndefinedInstruction::invoke(ThreadContext *tc)
}
void
-SupervisorCall::invoke(ThreadContext *tc)
+SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
{
// As of now, there isn't a 32 bit thumb version of this instruction.
assert(!machInst.bigThumb);
@@ -203,7 +203,7 @@ SupervisorCall::invoke(ThreadContext *tc)
template<class T>
void
-AbortFault<T>::invoke(ThreadContext *tc)
+AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
{
ArmFaultVals<T>::invoke(tc);
FSR fsr = 0;
@@ -217,7 +217,7 @@ AbortFault<T>::invoke(ThreadContext *tc)
}
void
-FlushPipe::invoke(ThreadContext *tc) {
+FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
DPRINTF(Faults, "Invoking FlushPipe Fault\n");
// Set the PC to the next instruction of the faulting instruction.
@@ -229,8 +229,10 @@ FlushPipe::invoke(ThreadContext *tc) {
tc->setNextMicroPC(1);
}
-template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc);
-template void AbortFault<DataAbort>::invoke(ThreadContext *tc);
+template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
+ StaticInstPtr inst);
+template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
+ StaticInstPtr inst);
// return via SUBS pc, lr, xxx; rfe, movs, ldm
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 3eef0e551..a68e7b2ef 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -108,7 +108,8 @@ class ArmFault : public FaultBase
};
#if FULL_SYSTEM
- void invoke(ThreadContext *tc);
+ void invoke(ThreadContext *tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
#endif
virtual FaultStat& countStat() = 0;
virtual FaultOffset offset() = 0;
@@ -140,7 +141,8 @@ class Reset : public ArmFaultVals<Reset>
#if FULL_SYSTEM
{
public:
- void invoke(ThreadContext *tc);
+ void invoke(ThreadContext *tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
#else
{};
@@ -165,7 +167,8 @@ class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
{
}
- void invoke(ThreadContext *tc);
+ void invoke(ThreadContext *tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
#endif
};
@@ -179,7 +182,8 @@ class SupervisorCall : public ArmFaultVals<SupervisorCall>
SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
{}
- void invoke(ThreadContext *tc);
+ void invoke(ThreadContext *tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
#endif
};
@@ -199,7 +203,8 @@ class AbortFault : public ArmFaultVals<T>
domain(_domain), status(_status)
{}
- void invoke(ThreadContext *tc);
+ void invoke(ThreadContext *tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
class PrefetchAbort : public AbortFault<PrefetchAbort>
@@ -232,7 +237,8 @@ class FlushPipe : public ArmFaultVals<FlushPipe>
{
public:
FlushPipe() {}
- void invoke(ThreadContext *tc);
+ void invoke(ThreadContext *tc,
+ StaticInstPtr inst = StaticInst::nullStaticInstPtr);
};
static inline Fault genMachineCheckFault()
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 5655c1265..22447184e 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -39,6 +39,7 @@
*/
#include "arch/arm/isa.hh"
+#include "sim/faults.hh"
namespace ArmISA
{
diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index b3ad567dc..111552c78 100644
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -59,6 +59,7 @@ output header {{
#include "arch/arm/insts/vfp.hh"
#include "arch/arm/isa_traits.hh"
#include "mem/packet.hh"
+#include "sim/faults.hh"
}};
output decoder {{
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index e426d6611..d97be88a2 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -45,6 +45,7 @@
#include "arch/arm/nativetrace.hh"
#include "cpu/thread_context.hh"
#include "params/ArmNativeTrace.hh"
+#include "sim/byteswap.hh"
namespace Trace {
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index e8dda1af0..636dd5310 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -50,6 +50,7 @@
#include "cpu/thread_context.hh"
#include "mem/page_table.hh"
#include "mem/translating_port.hh"
+#include "sim/byteswap.hh"
#include "sim/process_impl.hh"
#include "sim/system.hh"
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 680c93cba..141bd7138 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -48,8 +48,8 @@
#include "mem/request.hh"
#include "mem/request.hh"
#include "params/ArmTableWalker.hh"
-#include "sim/faults.hh"
#include "sim/eventq.hh"
+#include "sim/fault.hh"
class DmaPort;
class ThreadContext;
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 668984591..eec52d9d2 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -52,7 +52,7 @@
#include "base/statistics.hh"
#include "mem/request.hh"
#include "params/ArmTLB.hh"
-#include "sim/faults.hh"
+#include "sim/fault.hh"
#include "sim/tlb.hh"
class ThreadContext;
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 57b2423d3..2a30c5de2 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -48,6 +48,7 @@
#include "arch/arm/miscregs.hh"
#include "arch/arm/types.hh"
#include "base/hashmap.hh"
+#include "base/misc.hh"
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/thread_context.hh"
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 15:14:53 +0000