diff options
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa.cc | 41 | ||||
| -rw-r--r-- | src/arch/arm/isa.hh | 5 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.cc | 824 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 436 | ||||
| -rw-r--r-- | src/arch/arm/system.cc | 14 | ||||
| -rw-r--r-- | src/arch/arm/system.hh | 11 |
6 files changed, 1322 insertions, 9 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 647ecf787..d7d51b887 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -48,6 +48,8 @@ #include "debug/Arm.hh" #include "debug/MiscRegs.hh" #include "dev/arm/generic_timer.hh" +#include "dev/arm/gic_v3.hh" +#include "dev/arm/gic_v3_cpu_interface.hh" #include "params/ArmISA.hh" #include "sim/faults.hh" #include "sim/stat_control.hh" @@ -94,6 +96,13 @@ ISA::ISA(Params *p) physAddrRange = 32; // dummy value } + // GICv3 CPU interface system registers are supported + haveGICv3CPUInterface = false; + + if (system && dynamic_cast<Gicv3 *>(system->getGIC())) { + haveGICv3CPUInterface = true; + } + initializeMiscRegMetadata(); preUnflattenMiscReg(); @@ -372,6 +381,13 @@ ISA::startup(ThreadContext *tc) { pmu->setThreadContext(tc); + if (system) { + Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); + if (gicv3) { + gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); + gicv3CpuInterface->setISA(this); + } + } } @@ -672,10 +688,11 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) | (haveTimer ? 0x00010000 : 0x0); } case MISCREG_ID_AA64PFR0_EL1: - return 0x0000000000000002 // AArch{64,32} supported at EL0 - | 0x0000000000000020 // EL1 - | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 - | (haveSecurity ? 0x0000000000002000 : 0); // EL3 + return 0x0000000000000002 | // AArch{64,32} supported at EL0 + 0x0000000000000020 | // EL1 + (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 + (haveSecurity ? 0x0000000000002000 : 0) | // EL3 + (haveGICv3CPUInterface ? 0x0000000001000000 : 0); case MISCREG_ID_AA64PFR1_EL1: return 0; // bits [63:0] RES0 (reserved for future use) @@ -689,6 +706,10 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: return getGenericTimer(tc).readMiscReg(misc_reg); + case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: + case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: + return getGICv3CPUInterface(tc).readMiscReg(misc_reg); + default: break; @@ -1965,6 +1986,11 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: getGenericTimer(tc).setMiscReg(misc_reg, newVal); break; + + case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: + case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: + getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); + return; } } setMiscRegNoEffect(misc_reg, newVal); @@ -1991,6 +2017,13 @@ ISA::getGenericTimer(ThreadContext *tc) return *timer.get(); } +BaseISADevice & +ISA::getGICv3CPUInterface(ThreadContext *tc) +{ + panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); + return *gicv3CpuInterface.get(); +} + } ArmISA::ISA * diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 65d2251f8..1ec0f4676 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -82,6 +82,9 @@ namespace ArmISA // Generic timer interface belonging to this ISA std::unique_ptr<BaseISADevice> timer; + // GICv3 CPU interface belonging to this ISA + std::unique_ptr<BaseISADevice> gicv3CpuInterface; + // Cached copies of system-level properties bool highestELIs64; bool haveSecurity; @@ -89,6 +92,7 @@ namespace ArmISA bool haveVirtualization; bool haveCrypto; bool haveLargeAsid64; + bool haveGICv3CPUInterface; uint8_t physAddrRange; /** @@ -400,6 +404,7 @@ namespace ArmISA } BaseISADevice &getGenericTimer(ThreadContext *tc); + BaseISADevice &getGICv3CPUInterface(ThreadContext *tc); private: diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 7c1a6930c..1d4002a03 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -287,6 +287,11 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) return MISCREG_DACR; } break; + case 4: + if (opc1 == 0 && crm == 6 && opc2 == 0) { + return MISCREG_ICC_PMR; + } + break; case 5: if (opc1 == 0) { if (crm == 0) { @@ -668,10 +673,193 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) if (opc2 == 0) { return MISCREG_ISR; } + } else if (crm == 8) { + switch (opc2) { + case 0: + return MISCREG_ICC_IAR0; + case 1: + return MISCREG_ICC_EOIR0; + case 2: + return MISCREG_ICC_HPPIR0; + case 3: + return MISCREG_ICC_BPR0; + case 4: + return MISCREG_ICC_AP0R0; + case 5: + return MISCREG_ICC_AP0R1; + case 6: + return MISCREG_ICC_AP0R2; + case 7: + return MISCREG_ICC_AP0R3; + } + } else if (crm == 9) { + switch (opc2) { + case 0: + return MISCREG_ICC_AP1R0; + case 1: + return MISCREG_ICC_AP1R1; + case 2: + return MISCREG_ICC_AP1R2; + case 3: + return MISCREG_ICC_AP1R3; + } + } else if (crm == 11) { + switch (opc2) { + case 1: + return MISCREG_ICC_DIR; + case 3: + return MISCREG_ICC_RPR; + } + } else if (crm == 12) { + switch (opc2) { + case 0: + return MISCREG_ICC_IAR1; + case 1: + return MISCREG_ICC_EOIR1; + case 2: + return MISCREG_ICC_HPPIR1; + case 3: + return MISCREG_ICC_BPR1; + case 4: + return MISCREG_ICC_CTLR; + case 5: + return MISCREG_ICC_SRE; + case 6: + return MISCREG_ICC_IGRPEN0; + case 7: + return MISCREG_ICC_IGRPEN1; + } } } else if (opc1 == 4) { - if (crm == 0 && opc2 == 0) + if (crm == 0 && opc2 == 0) { return MISCREG_HVBAR; + } else if (crm == 8) { + switch (opc2) { + case 0: + return MISCREG_ICH_AP0R0; + case 1: + return MISCREG_ICH_AP0R1; + case 2: + return MISCREG_ICH_AP0R2; + case 3: + return MISCREG_ICH_AP0R3; + } + } else if (crm == 9) { + switch (opc2) { + case 0: + return MISCREG_ICH_AP1R0; + case 1: + return MISCREG_ICH_AP1R1; + case 2: + return MISCREG_ICH_AP1R2; + case 3: + return MISCREG_ICH_AP1R3; + case 5: + return MISCREG_ICC_HSRE; + } + } else if (crm == 11) { + switch (opc2) { + case 0: + return MISCREG_ICH_HCR; + case 1: + return MISCREG_ICH_VTR; + case 2: + return MISCREG_ICH_MISR; + case 3: + return MISCREG_ICH_EISR; + case 5: + return MISCREG_ICH_ELRSR; + case 7: + return MISCREG_ICH_VMCR; + } + } else if (crm == 12) { + switch (opc2) { + case 0: + return MISCREG_ICH_LR0; + case 1: + return MISCREG_ICH_LR1; + case 2: + return MISCREG_ICH_LR2; + case 3: + return MISCREG_ICH_LR3; + case 4: + return MISCREG_ICH_LR4; + case 5: + return MISCREG_ICH_LR5; + case 6: + return MISCREG_ICH_LR6; + case 7: + return MISCREG_ICH_LR7; + } + } else if (crm == 13) { + switch (opc2) { + case 0: + return MISCREG_ICH_LR8; + case 1: + return MISCREG_ICH_LR9; + case 2: + return MISCREG_ICH_LR10; + case 3: + return MISCREG_ICH_LR11; + case 4: + return MISCREG_ICH_LR12; + case 5: + return MISCREG_ICH_LR13; + case 6: + return MISCREG_ICH_LR14; + case 7: + return MISCREG_ICH_LR15; + } + } else if (crm == 14) { + switch (opc2) { + case 0: + return MISCREG_ICH_LRC0; + case 1: + return MISCREG_ICH_LRC1; + case 2: + return MISCREG_ICH_LRC2; + case 3: + return MISCREG_ICH_LRC3; + case 4: + return MISCREG_ICH_LRC4; + case 5: + return MISCREG_ICH_LRC5; + case 6: + return MISCREG_ICH_LRC6; + case 7: + return MISCREG_ICH_LRC7; + } + } else if (crm == 15) { + switch (opc2) { + case 0: + return MISCREG_ICH_LRC8; + case 1: + return MISCREG_ICH_LRC9; + case 2: + return MISCREG_ICH_LRC10; + case 3: + return MISCREG_ICH_LRC11; + case 4: + return MISCREG_ICH_LRC12; + case 5: + return MISCREG_ICH_LRC13; + case 6: + return MISCREG_ICH_LRC14; + case 7: + return MISCREG_ICH_LRC15; + } + } + } else if (opc1 == 6) { + if (crm == 12) { + switch (opc2) { + case 4: + return MISCREG_ICC_MCTLR; + case 5: + return MISCREG_ICC_MSRE; + case 7: + return MISCREG_ICC_MGRPEN1; + } + } } break; case 13: @@ -1766,6 +1954,12 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, return MISCREG_CURRENTEL; } break; + case 6: + switch (op2) { + case 0: + return MISCREG_ICC_PMR_EL1; + } + break; } break; case 3: @@ -2145,6 +2339,72 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, return MISCREG_DISR_EL1; } break; + case 8: + switch (op2) { + case 0: + return MISCREG_ICC_IAR0_EL1; + case 1: + return MISCREG_ICC_EOIR0_EL1; + case 2: + return MISCREG_ICC_HPPIR0_EL1; + case 3: + return MISCREG_ICC_BPR0_EL1; + case 4: + return MISCREG_ICC_AP0R0_EL1; + case 5: + return MISCREG_ICC_AP0R1_EL1; + case 6: + return MISCREG_ICC_AP0R2_EL1; + case 7: + return MISCREG_ICC_AP0R3_EL1; + } + break; + case 9: + switch (op2) { + case 0: + return MISCREG_ICC_AP1R0_EL1; + case 1: + return MISCREG_ICC_AP1R1_EL1; + case 2: + return MISCREG_ICC_AP1R2_EL1; + case 3: + return MISCREG_ICC_AP1R3_EL1; + } + break; + case 11: + switch (op2) { + case 1: + return MISCREG_ICC_DIR_EL1; + case 3: + return MISCREG_ICC_RPR_EL1; + case 5: + return MISCREG_ICC_SGI1R_EL1; + case 6: + return MISCREG_ICC_ASGI1R_EL1; + case 7: + return MISCREG_ICC_SGI0R_EL1; + } + break; + case 12: + switch (op2) { + case 0: + return MISCREG_ICC_IAR1_EL1; + case 1: + return MISCREG_ICC_EOIR1_EL1; + case 2: + return MISCREG_ICC_HPPIR1_EL1; + case 3: + return MISCREG_ICC_BPR1_EL1; + case 4: + return MISCREG_ICC_CTLR_EL1; + case 5: + return MISCREG_ICC_SRE_EL1; + case 6: + return MISCREG_ICC_IGRPEN0_EL1; + case 7: + return MISCREG_ICC_IGRPEN1_EL1; + } + break; } break; case 4: @@ -2163,6 +2423,88 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, return MISCREG_VDISR_EL2; } break; + case 8: + switch (op2) { + case 0: + return MISCREG_ICH_AP0R0_EL2; + case 1: + return MISCREG_ICH_AP0R1_EL2; + case 2: + return MISCREG_ICH_AP0R2_EL2; + case 3: + return MISCREG_ICH_AP0R3_EL2; + } + break; + case 9: + switch (op2) { + case 0: + return MISCREG_ICH_AP1R0_EL2; + case 1: + return MISCREG_ICH_AP1R1_EL2; + case 2: + return MISCREG_ICH_AP1R2_EL2; + case 3: + return MISCREG_ICH_AP1R3_EL2; + case 5: + return MISCREG_ICC_SRE_EL2; + } + break; + case 11: + switch (op2) { + case 0: + return MISCREG_ICH_HCR_EL2; + case 1: + return MISCREG_ICH_VTR_EL2; + case 2: + return MISCREG_ICH_MISR_EL2; + case 3: + return MISCREG_ICH_EISR_EL2; + case 5: + return MISCREG_ICH_ELRSR_EL2; + case 7: + return MISCREG_ICH_VMCR_EL2; + } + break; + case 12: + switch (op2) { + case 0: + return MISCREG_ICH_LR0_EL2; + case 1: + return MISCREG_ICH_LR1_EL2; + case 2: + return MISCREG_ICH_LR2_EL2; + case 3: + return MISCREG_ICH_LR3_EL2; + case 4: + return MISCREG_ICH_LR4_EL2; + case 5: + return MISCREG_ICH_LR5_EL2; + case 6: + return MISCREG_ICH_LR6_EL2; + case 7: + return MISCREG_ICH_LR7_EL2; + } + break; + case 13: + switch (op2) { + case 0: + return MISCREG_ICH_LR8_EL2; + case 1: + return MISCREG_ICH_LR9_EL2; + case 2: + return MISCREG_ICH_LR10_EL2; + case 3: + return MISCREG_ICH_LR11_EL2; + case 4: + return MISCREG_ICH_LR12_EL2; + case 5: + return MISCREG_ICH_LR13_EL2; + case 6: + return MISCREG_ICH_LR14_EL2; + case 7: + return MISCREG_ICH_LR15_EL2; + } + break; } break; case 6: @@ -2177,6 +2519,16 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, return MISCREG_RMR_EL3; } break; + case 12: + switch (op2) { + case 4: + return MISCREG_ICC_CTLR_EL3; + case 5: + return MISCREG_ICC_SRE_EL3; + case 7: + return MISCREG_ICC_IGRPEN1_EL3; + } + break; } break; } @@ -4094,6 +4446,476 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_CONTEXTIDR_EL2) .mon().hyp(); + + // GICv3 AArch64 + InitReg(MISCREG_ICC_PMR_EL1) + .res0(0xffffff00) // [31:8] + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_PMR); + InitReg(MISCREG_ICC_IAR0_EL1) + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ICC_IAR0); + InitReg(MISCREG_ICC_EOIR0_EL1) + .allPrivileges().exceptUserMode().reads(0) + .mapsTo(MISCREG_ICC_EOIR0); + InitReg(MISCREG_ICC_HPPIR0_EL1) + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ICC_HPPIR0); + InitReg(MISCREG_ICC_BPR0_EL1) + .res0(0xfffffff8) // [31:3] + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_BPR0); + InitReg(MISCREG_ICC_AP0R0_EL1) + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_AP0R0); + InitReg(MISCREG_ICC_AP0R1_EL1) + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_AP0R1); + InitReg(MISCREG_ICC_AP0R2_EL1) + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_AP0R2); + InitReg(MISCREG_ICC_AP0R3_EL1) + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_AP0R3); + InitReg(MISCREG_ICC_AP1R0_EL1) + .banked() + .mapsTo(MISCREG_ICC_AP1R0); + InitReg(MISCREG_ICC_AP1R0_EL1_NS) + .bankedChild() + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_AP1R0_NS); + InitReg(MISCREG_ICC_AP1R0_EL1_S) + .bankedChild() + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_AP1R0_S); + InitReg(MISCREG_ICC_AP1R1_EL1) + .banked() + .mapsTo(MISCREG_ICC_AP1R1); + InitReg(MISCREG_ICC_AP1R1_EL1_NS) + .bankedChild() + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_AP1R1_NS); + InitReg(MISCREG_ICC_AP1R1_EL1_S) + .bankedChild() + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_AP1R1_S); + InitReg(MISCREG_ICC_AP1R2_EL1) + .banked() + .mapsTo(MISCREG_ICC_AP1R2); + InitReg(MISCREG_ICC_AP1R2_EL1_NS) + .bankedChild() + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_AP1R2_NS); + InitReg(MISCREG_ICC_AP1R2_EL1_S) + .bankedChild() + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_AP1R2_S); + InitReg(MISCREG_ICC_AP1R3_EL1) + .banked() + .mapsTo(MISCREG_ICC_AP1R3); + InitReg(MISCREG_ICC_AP1R3_EL1_NS) + .bankedChild() + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_AP1R3_NS); + InitReg(MISCREG_ICC_AP1R3_EL1_S) + .bankedChild() + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_AP1R3_S); + InitReg(MISCREG_ICC_DIR_EL1) + .res0(0xFF000000) // [31:24] + .allPrivileges().exceptUserMode().reads(0) + .mapsTo(MISCREG_ICC_DIR); + InitReg(MISCREG_ICC_RPR_EL1) + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ICC_RPR); + InitReg(MISCREG_ICC_SGI1R_EL1) + .allPrivileges().exceptUserMode().reads(0) + .mapsTo(MISCREG_ICC_SGI1R); + InitReg(MISCREG_ICC_ASGI1R_EL1) + .allPrivileges().exceptUserMode().reads(0) + .mapsTo(MISCREG_ICC_ASGI1R); + InitReg(MISCREG_ICC_SGI0R_EL1) + .allPrivileges().exceptUserMode().reads(0) + .mapsTo(MISCREG_ICC_SGI0R); + InitReg(MISCREG_ICC_IAR1_EL1) + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ICC_IAR1); + InitReg(MISCREG_ICC_EOIR1_EL1) + .res0(0xFF000000) // [31:24] + .allPrivileges().exceptUserMode().reads(0) + .mapsTo(MISCREG_ICC_EOIR1); + InitReg(MISCREG_ICC_HPPIR1_EL1) + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ICC_HPPIR1); + InitReg(MISCREG_ICC_BPR1_EL1) + .banked() + .mapsTo(MISCREG_ICC_BPR1); + InitReg(MISCREG_ICC_BPR1_EL1_NS) + .bankedChild() + .res0(0xfffffff8) // [31:3] + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_BPR1_NS); + InitReg(MISCREG_ICC_BPR1_EL1_S) + .bankedChild() + .res0(0xfffffff8) // [31:3] + .secure().exceptUserMode() + .mapsTo(MISCREG_ICC_BPR1_S); + InitReg(MISCREG_ICC_CTLR_EL1) + .banked() + .mapsTo(MISCREG_ICC_CTLR); + InitReg(MISCREG_ICC_CTLR_EL1_NS) + .bankedChild() + .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2] + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_CTLR_NS); + InitReg(MISCREG_ICC_CTLR_EL1_S) + .bankedChild() + .res0(0xFFFB00BC) // [31:19, 17:16, 7, 5:2] + .secure().exceptUserMode() + .mapsTo(MISCREG_ICC_CTLR_S); + InitReg(MISCREG_ICC_SRE_EL1) + .banked() + .mapsTo(MISCREG_ICC_SRE); + InitReg(MISCREG_ICC_SRE_EL1_NS) + .bankedChild() + .res0(0xFFFFFFF8) // [31:3] + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_SRE_NS); + InitReg(MISCREG_ICC_SRE_EL1_S) + .bankedChild() + .res0(0xFFFFFFF8) // [31:3] + .secure().exceptUserMode() + .mapsTo(MISCREG_ICC_SRE_S); + InitReg(MISCREG_ICC_IGRPEN0_EL1) + .res0(0xFFFFFFFE) // [31:1] + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_IGRPEN0); + InitReg(MISCREG_ICC_IGRPEN1_EL1) + .banked() + .mapsTo(MISCREG_ICC_IGRPEN1); + InitReg(MISCREG_ICC_IGRPEN1_EL1_NS) + .bankedChild() + .res0(0xFFFFFFFE) // [31:1] + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_IGRPEN1_NS); + InitReg(MISCREG_ICC_IGRPEN1_EL1_S) + .bankedChild() + .res0(0xFFFFFFFE) // [31:1] + .secure().exceptUserMode() + .mapsTo(MISCREG_ICC_IGRPEN1_S); + InitReg(MISCREG_ICC_SRE_EL2) + .hyp().mon() + .mapsTo(MISCREG_ICC_HSRE); + InitReg(MISCREG_ICC_CTLR_EL3) + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_MCTLR); + InitReg(MISCREG_ICC_SRE_EL3) + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_MSRE); + InitReg(MISCREG_ICC_IGRPEN1_EL3) + .allPrivileges().exceptUserMode() + .mapsTo(MISCREG_ICC_MGRPEN1); + + InitReg(MISCREG_ICH_AP0R0_EL2) + .hyp().mon() + .mapsTo(MISCREG_ICH_AP0R0); + InitReg(MISCREG_ICH_AP0R1_EL2) + .hyp().mon() + .unimplemented() + .mapsTo(MISCREG_ICH_AP0R1); + InitReg(MISCREG_ICH_AP0R2_EL2) + .hyp().mon() + .unimplemented() + .mapsTo(MISCREG_ICH_AP0R2); + InitReg(MISCREG_ICH_AP0R3_EL2) + .hyp().mon() + .unimplemented() + .mapsTo(MISCREG_ICH_AP0R3); + InitReg(MISCREG_ICH_AP1R0_EL2) + .hyp().mon() + .mapsTo(MISCREG_ICH_AP1R0); + InitReg(MISCREG_ICH_AP1R1_EL2) + .hyp().mon() + .unimplemented() + .mapsTo(MISCREG_ICH_AP1R1); + InitReg(MISCREG_ICH_AP1R2_EL2) + .hyp().mon() + .unimplemented() + .mapsTo(MISCREG_ICH_AP1R2); + InitReg(MISCREG_ICH_AP1R3_EL2) + .hyp().mon() + .unimplemented() + .mapsTo(MISCREG_ICH_AP1R3); + InitReg(MISCREG_ICH_HCR_EL2) + .hyp().mon() + .mapsTo(MISCREG_ICH_HCR); + InitReg(MISCREG_ICH_VTR_EL2) + .hyp().mon().writes(0) + .mapsTo(MISCREG_ICH_VTR); + InitReg(MISCREG_ICH_MISR_EL2) + .hyp().mon().writes(0) + .mapsTo(MISCREG_ICH_MISR); + InitReg(MISCREG_ICH_EISR_EL2) + .hyp().mon().writes(0) + .mapsTo(MISCREG_ICH_EISR); + InitReg(MISCREG_ICH_ELRSR_EL2) + .hyp().mon().writes(0) + .mapsTo(MISCREG_ICH_ELRSR); + InitReg(MISCREG_ICH_VMCR_EL2) + .hyp().mon() + .mapsTo(MISCREG_ICH_VMCR); + InitReg(MISCREG_ICH_LR0_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR1_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR2_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR3_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR4_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR5_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR6_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR7_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR8_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR9_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR10_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR11_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR12_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR13_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR14_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICH_LR15_EL2) + .hyp().mon() + .allPrivileges().exceptUserMode(); + + // GICv3 AArch32 + InitReg(MISCREG_ICC_AP0R0) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP0R1) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP0R2) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP0R3) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP1R0) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP1R0_NS) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP1R0_S) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP1R1) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP1R1_NS) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP1R1_S) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP1R2) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP1R2_NS) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP1R2_S) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP1R3) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP1R3_NS) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_AP1R3_S) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_ASGI1R) + .allPrivileges().exceptUserMode().reads(0); + InitReg(MISCREG_ICC_BPR0) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_BPR1) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_BPR1_NS) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_BPR1_S) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_CTLR) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_CTLR_NS) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_CTLR_S) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_DIR) + .allPrivileges().exceptUserMode().reads(0); + InitReg(MISCREG_ICC_EOIR0) + .allPrivileges().exceptUserMode().reads(0); + InitReg(MISCREG_ICC_EOIR1) + .allPrivileges().exceptUserMode().reads(0); + InitReg(MISCREG_ICC_HPPIR0) + .allPrivileges().exceptUserMode().writes(0); + InitReg(MISCREG_ICC_HPPIR1) + .allPrivileges().exceptUserMode().writes(0); + InitReg(MISCREG_ICC_HSRE) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_IAR0) + .allPrivileges().exceptUserMode().writes(0); + InitReg(MISCREG_ICC_IAR1) + .allPrivileges().exceptUserMode().writes(0); + InitReg(MISCREG_ICC_IGRPEN0) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_IGRPEN1) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_IGRPEN1_NS) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_IGRPEN1_S) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_MCTLR) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_MGRPEN1) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_MSRE) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_PMR) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_RPR) + .allPrivileges().exceptUserMode().writes(0); + InitReg(MISCREG_ICC_SGI0R) + .allPrivileges().exceptUserMode().reads(0); + InitReg(MISCREG_ICC_SGI1R) + .allPrivileges().exceptUserMode().reads(0); + InitReg(MISCREG_ICC_SRE) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_SRE_NS) + .allPrivileges().exceptUserMode(); + InitReg(MISCREG_ICC_SRE_S) + .allPrivileges().exceptUserMode(); + + InitReg(MISCREG_ICH_AP0R0) + .hyp().mon(); + InitReg(MISCREG_ICH_AP0R1) + .hyp().mon(); + InitReg(MISCREG_ICH_AP0R2) + .hyp().mon(); + InitReg(MISCREG_ICH_AP0R3) + .hyp().mon(); + InitReg(MISCREG_ICH_AP1R0) + .hyp().mon(); + InitReg(MISCREG_ICH_AP1R1) + .hyp().mon(); + InitReg(MISCREG_ICH_AP1R2) + .hyp().mon(); + InitReg(MISCREG_ICH_AP1R3) + .hyp().mon(); + InitReg(MISCREG_ICH_HCR) + .hyp().mon(); + InitReg(MISCREG_ICH_VTR) + .hyp().mon().writes(0); + InitReg(MISCREG_ICH_MISR) + .hyp().mon().writes(0); + InitReg(MISCREG_ICH_EISR) + .hyp().mon().writes(0); + InitReg(MISCREG_ICH_ELRSR) + .hyp().mon().writes(0); + InitReg(MISCREG_ICH_VMCR) + .hyp().mon(); + InitReg(MISCREG_ICH_LR0) + .hyp().mon(); + InitReg(MISCREG_ICH_LR1) + .hyp().mon(); + InitReg(MISCREG_ICH_LR2) + .hyp().mon(); + InitReg(MISCREG_ICH_LR3) + .hyp().mon(); + InitReg(MISCREG_ICH_LR4) + .hyp().mon(); + InitReg(MISCREG_ICH_LR5) + .hyp().mon(); + InitReg(MISCREG_ICH_LR6) + .hyp().mon(); + InitReg(MISCREG_ICH_LR7) + .hyp().mon(); + InitReg(MISCREG_ICH_LR8) + .hyp().mon(); + InitReg(MISCREG_ICH_LR9) + .hyp().mon(); + InitReg(MISCREG_ICH_LR10) + .hyp().mon(); + InitReg(MISCREG_ICH_LR11) + .hyp().mon(); + InitReg(MISCREG_ICH_LR12) + .hyp().mon(); + InitReg(MISCREG_ICH_LR13) + .hyp().mon(); + InitReg(MISCREG_ICH_LR14) + .hyp().mon(); + InitReg(MISCREG_ICH_LR15) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC0) + .mapsTo(MISCREG_ICH_LR0) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC1) + .mapsTo(MISCREG_ICH_LR1) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC2) + .mapsTo(MISCREG_ICH_LR2) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC3) + .mapsTo(MISCREG_ICH_LR3) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC4) + .mapsTo(MISCREG_ICH_LR4) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC5) + .mapsTo(MISCREG_ICH_LR5) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC6) + .mapsTo(MISCREG_ICH_LR6) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC7) + .mapsTo(MISCREG_ICH_LR7) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC8) + .mapsTo(MISCREG_ICH_LR8) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC9) + .mapsTo(MISCREG_ICH_LR9) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC10) + .mapsTo(MISCREG_ICH_LR10) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC11) + .mapsTo(MISCREG_ICH_LR11) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC12) + .mapsTo(MISCREG_ICH_LR12) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC13) + .mapsTo(MISCREG_ICH_LR13) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC14) + .mapsTo(MISCREG_ICH_LR14) + .hyp().mon(); + InitReg(MISCREG_ICH_LRC15) + .mapsTo(MISCREG_ICH_LR15) + .hyp().mon(); + InitReg(MISCREG_CNTHV_CTL_EL2) .mon().hyp(); InitReg(MISCREG_CNTHV_CVAL_EL2) diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index dcaaa7fe3..0d40b27a4 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -673,6 +673,224 @@ namespace ArmISA MISCREG_CNTHV_TVAL_EL2, MISCREG_ID_AA64MMFR2_EL1, + + // GICv3, CPU interface + MISCREG_ICC_PMR_EL1, + MISCREG_ICC_IAR0_EL1, + MISCREG_ICC_EOIR0_EL1, + MISCREG_ICC_HPPIR0_EL1, + MISCREG_ICC_BPR0_EL1, + MISCREG_ICC_AP0R0_EL1, + MISCREG_ICC_AP0R1_EL1, + MISCREG_ICC_AP0R2_EL1, + MISCREG_ICC_AP0R3_EL1, + MISCREG_ICC_AP1R0_EL1, + MISCREG_ICC_AP1R0_EL1_NS, + MISCREG_ICC_AP1R0_EL1_S, + MISCREG_ICC_AP1R1_EL1, + MISCREG_ICC_AP1R1_EL1_NS, + MISCREG_ICC_AP1R1_EL1_S, + MISCREG_ICC_AP1R2_EL1, + MISCREG_ICC_AP1R2_EL1_NS, + MISCREG_ICC_AP1R2_EL1_S, + MISCREG_ICC_AP1R3_EL1, + MISCREG_ICC_AP1R3_EL1_NS, + MISCREG_ICC_AP1R3_EL1_S, + MISCREG_ICC_DIR_EL1, + MISCREG_ICC_RPR_EL1, + MISCREG_ICC_SGI1R_EL1, + MISCREG_ICC_ASGI1R_EL1, + MISCREG_ICC_SGI0R_EL1, + MISCREG_ICC_IAR1_EL1, + MISCREG_ICC_EOIR1_EL1, + MISCREG_ICC_HPPIR1_EL1, + MISCREG_ICC_BPR1_EL1, + MISCREG_ICC_BPR1_EL1_NS, + MISCREG_ICC_BPR1_EL1_S, + MISCREG_ICC_CTLR_EL1, + MISCREG_ICC_CTLR_EL1_NS, + MISCREG_ICC_CTLR_EL1_S, + MISCREG_ICC_SRE_EL1, + MISCREG_ICC_SRE_EL1_NS, + MISCREG_ICC_SRE_EL1_S, + MISCREG_ICC_IGRPEN0_EL1, + MISCREG_ICC_IGRPEN1_EL1, + MISCREG_ICC_IGRPEN1_EL1_NS, + MISCREG_ICC_IGRPEN1_EL1_S, + MISCREG_ICC_SRE_EL2, + MISCREG_ICC_CTLR_EL3, + MISCREG_ICC_SRE_EL3, + MISCREG_ICC_IGRPEN1_EL3, + + // GICv3, CPU interface, virtualization + MISCREG_ICH_AP0R0_EL2, + MISCREG_ICH_AP0R1_EL2, + MISCREG_ICH_AP0R2_EL2, + MISCREG_ICH_AP0R3_EL2, + MISCREG_ICH_AP1R0_EL2, + MISCREG_ICH_AP1R1_EL2, + MISCREG_ICH_AP1R2_EL2, + MISCREG_ICH_AP1R3_EL2, + MISCREG_ICH_HCR_EL2, + MISCREG_ICH_VTR_EL2, + MISCREG_ICH_MISR_EL2, + MISCREG_ICH_EISR_EL2, + MISCREG_ICH_ELRSR_EL2, + MISCREG_ICH_VMCR_EL2, + MISCREG_ICH_LR0_EL2, + MISCREG_ICH_LR1_EL2, + MISCREG_ICH_LR2_EL2, + MISCREG_ICH_LR3_EL2, + MISCREG_ICH_LR4_EL2, + MISCREG_ICH_LR5_EL2, + MISCREG_ICH_LR6_EL2, + MISCREG_ICH_LR7_EL2, + MISCREG_ICH_LR8_EL2, + MISCREG_ICH_LR9_EL2, + MISCREG_ICH_LR10_EL2, + MISCREG_ICH_LR11_EL2, + MISCREG_ICH_LR12_EL2, + MISCREG_ICH_LR13_EL2, + MISCREG_ICH_LR14_EL2, + MISCREG_ICH_LR15_EL2, + + MISCREG_ICV_PMR_EL1, + MISCREG_ICV_IAR0_EL1, + MISCREG_ICV_EOIR0_EL1, + MISCREG_ICV_HPPIR0_EL1, + MISCREG_ICV_BPR0_EL1, + MISCREG_ICV_AP0R0_EL1, + MISCREG_ICV_AP0R1_EL1, + MISCREG_ICV_AP0R2_EL1, + MISCREG_ICV_AP0R3_EL1, + MISCREG_ICV_AP1R0_EL1, + MISCREG_ICV_AP1R0_EL1_NS, + MISCREG_ICV_AP1R0_EL1_S, + MISCREG_ICV_AP1R1_EL1, + MISCREG_ICV_AP1R1_EL1_NS, + MISCREG_ICV_AP1R1_EL1_S, + MISCREG_ICV_AP1R2_EL1, + MISCREG_ICV_AP1R2_EL1_NS, + MISCREG_ICV_AP1R2_EL1_S, + MISCREG_ICV_AP1R3_EL1, + MISCREG_ICV_AP1R3_EL1_NS, + MISCREG_ICV_AP1R3_EL1_S, + MISCREG_ICV_DIR_EL1, + MISCREG_ICV_RPR_EL1, + MISCREG_ICV_SGI1R_EL1, + MISCREG_ICV_ASGI1R_EL1, + MISCREG_ICV_SGI0R_EL1, + MISCREG_ICV_IAR1_EL1, + MISCREG_ICV_EOIR1_EL1, + MISCREG_ICV_HPPIR1_EL1, + MISCREG_ICV_BPR1_EL1, + MISCREG_ICV_BPR1_EL1_NS, + MISCREG_ICV_BPR1_EL1_S, + MISCREG_ICV_CTLR_EL1, + MISCREG_ICV_CTLR_EL1_NS, + MISCREG_ICV_CTLR_EL1_S, + MISCREG_ICV_SRE_EL1, + MISCREG_ICV_SRE_EL1_NS, + MISCREG_ICV_SRE_EL1_S, + MISCREG_ICV_IGRPEN0_EL1, + MISCREG_ICV_IGRPEN1_EL1, + MISCREG_ICV_IGRPEN1_EL1_NS, + MISCREG_ICV_IGRPEN1_EL1_S, + + MISCREG_ICC_AP0R0, + MISCREG_ICC_AP0R1, + MISCREG_ICC_AP0R2, + MISCREG_ICC_AP0R3, + MISCREG_ICC_AP1R0, + MISCREG_ICC_AP1R0_NS, + MISCREG_ICC_AP1R0_S, + MISCREG_ICC_AP1R1, + MISCREG_ICC_AP1R1_NS, + MISCREG_ICC_AP1R1_S, + MISCREG_ICC_AP1R2, + MISCREG_ICC_AP1R2_NS, + MISCREG_ICC_AP1R2_S, + MISCREG_ICC_AP1R3, + MISCREG_ICC_AP1R3_NS, + MISCREG_ICC_AP1R3_S, + MISCREG_ICC_ASGI1R, + MISCREG_ICC_BPR0, + MISCREG_ICC_BPR1, + MISCREG_ICC_BPR1_NS, + MISCREG_ICC_BPR1_S, + MISCREG_ICC_CTLR, + MISCREG_ICC_CTLR_NS, + MISCREG_ICC_CTLR_S, + MISCREG_ICC_DIR, + MISCREG_ICC_EOIR0, + MISCREG_ICC_EOIR1, + MISCREG_ICC_HPPIR0, + MISCREG_ICC_HPPIR1, + MISCREG_ICC_HSRE, + MISCREG_ICC_IAR0, + MISCREG_ICC_IAR1, + MISCREG_ICC_IGRPEN0, + MISCREG_ICC_IGRPEN1, + MISCREG_ICC_IGRPEN1_NS, + MISCREG_ICC_IGRPEN1_S, + MISCREG_ICC_MCTLR, + MISCREG_ICC_MGRPEN1, + MISCREG_ICC_MSRE, + MISCREG_ICC_PMR, + MISCREG_ICC_RPR, + MISCREG_ICC_SGI0R, + MISCREG_ICC_SGI1R, + MISCREG_ICC_SRE, + MISCREG_ICC_SRE_NS, + MISCREG_ICC_SRE_S, + + MISCREG_ICH_AP0R0, + MISCREG_ICH_AP0R1, + MISCREG_ICH_AP0R2, + MISCREG_ICH_AP0R3, + MISCREG_ICH_AP1R0, + MISCREG_ICH_AP1R1, + MISCREG_ICH_AP1R2, + MISCREG_ICH_AP1R3, + MISCREG_ICH_HCR, + MISCREG_ICH_VTR, + MISCREG_ICH_MISR, + MISCREG_ICH_EISR, + MISCREG_ICH_ELRSR, + MISCREG_ICH_VMCR, + MISCREG_ICH_LR0, + MISCREG_ICH_LR1, + MISCREG_ICH_LR2, + MISCREG_ICH_LR3, + MISCREG_ICH_LR4, + MISCREG_ICH_LR5, + MISCREG_ICH_LR6, + MISCREG_ICH_LR7, + MISCREG_ICH_LR8, + MISCREG_ICH_LR9, + MISCREG_ICH_LR10, + MISCREG_ICH_LR11, + MISCREG_ICH_LR12, + MISCREG_ICH_LR13, + MISCREG_ICH_LR14, + MISCREG_ICH_LR15, + MISCREG_ICH_LRC0, + MISCREG_ICH_LRC1, + MISCREG_ICH_LRC2, + MISCREG_ICH_LRC3, + MISCREG_ICH_LRC4, + MISCREG_ICH_LRC5, + MISCREG_ICH_LRC6, + MISCREG_ICH_LRC7, + MISCREG_ICH_LRC8, + MISCREG_ICH_LRC9, + MISCREG_ICH_LRC10, + MISCREG_ICH_LRC11, + MISCREG_ICH_LRC12, + MISCREG_ICH_LRC13, + MISCREG_ICH_LRC14, + MISCREG_ICH_LRC15, + // These MISCREG_FREESLOT are available Misc Register // slots for future registers to be implemented. MISCREG_FREESLOT_1, @@ -1389,6 +1607,224 @@ namespace ArmISA "cnthv_cval_el2", "cnthv_tval_el2", "id_aa64mmfr2_el1", + + // GICv3, CPU interface + "icc_pmr_el1", + "icc_iar0_el1", + "icc_eoir0_el1", + "icc_hppir0_el1", + "icc_bpr0_el1", + "icc_ap0r0_el1", + "icc_ap0r1_el1", + "icc_ap0r2_el1", + "icc_ap0r3_el1", + "icc_ap1r0_el1", + "icc_ap1r0_el1_ns", + "icc_ap1r0_el1_s", + "icc_ap1r1_el1", + "icc_ap1r1_el1_ns", + "icc_ap1r1_el1_s", + "icc_ap1r2_el1", + "icc_ap1r2_el1_ns", + "icc_ap1r2_el1_s", + "icc_ap1r3_el1", + "icc_ap1r3_el1_ns", + "icc_ap1r3_el1_s", + "icc_dir_el1", + "icc_rpr_el1", + "icc_sgi1r_el1", + "icc_asgi1r_el1", + "icc_sgi0r_el1", + "icc_iar1_el1", + "icc_eoir1_el1", + "icc_hppir1_el1", + "icc_bpr1_el1", + "icc_bpr1_el1_ns", + "icc_bpr1_el1_s", + "icc_ctlr_el1", + "icc_ctlr_el1_ns", + "icc_ctlr_el1_s", + "icc_sre_el1", + "icc_sre_el1_ns", + "icc_sre_el1_s", + "icc_igrpen0_el1", + "icc_igrpen1_el1", + "icc_igrpen1_el1_ns", + "icc_igrpen1_el1_s", + "icc_sre_el2", + "icc_ctlr_el3", + "icc_sre_el3", + "icc_igrpen1_el3", + + // GICv3, CPU interface, virtualization + "ich_ap0r0_el2", + "ich_ap0r1_el2", + "ich_ap0r2_el2", + "ich_ap0r3_el2", + "ich_ap1r0_el2", + "ich_ap1r1_el2", + "ich_ap1r2_el2", + "ich_ap1r3_el2", + "ich_hcr_el2", + "ich_vtr_el2", + "ich_misr_el2", + "ich_eisr_el2", + "ich_elrsr_el2", + "ich_vmcr_el2", + "ich_lr0_el2", + "ich_lr1_el2", + "ich_lr2_el2", + "ich_lr3_el2", + "ich_lr4_el2", + "ich_lr5_el2", + "ich_lr6_el2", + "ich_lr7_el2", + "ich_lr8_el2", + "ich_lr9_el2", + "ich_lr10_el2", + "ich_lr11_el2", + "ich_lr12_el2", + "ich_lr13_el2", + "ich_lr14_el2", + "ich_lr15_el2", + + "icv_pmr_el1", + "icv_iar0_el1", + "icv_eoir0_el1", + "icv_hppir0_el1", + "icv_bpr0_el1", + "icv_ap0r0_el1", + "icv_ap0r1_el1", + "icv_ap0r2_el1", + "icv_ap0r3_el1", + "icv_ap1r0_el1", + "icv_ap1r0_el1_ns", + "icv_ap1r0_el1_s", + "icv_ap1r1_el1", + "icv_ap1r1_el1_ns", + "icv_ap1r1_el1_s", + "icv_ap1r2_el1", + "icv_ap1r2_el1_ns", + "icv_ap1r2_el1_s", + "icv_ap1r3_el1", + "icv_ap1r3_el1_ns", + "icv_ap1r3_el1_s", + "icv_dir_el1", + "icv_rpr_el1", + "icv_sgi1r_el1", + "icv_asgi1r_el1", + "icv_sgi0r_el1", + "icv_iar1_el1", + "icv_eoir1_el1", + "icv_hppir1_el1", + "icv_bpr1_el1", + "icv_bpr1_el1_ns", + "icv_bpr1_el1_s", + "icv_ctlr_el1", + "icv_ctlr_el1_ns", + "icv_ctlr_el1_s", + "icv_sre_el1", + "icv_sre_el1_ns", + "icv_sre_el1_s", + "icv_igrpen0_el1", + "icv_igrpen1_el1", + "icv_igrpen1_el1_ns", + "icv_igrpen1_el1_s", + + "icc_ap0r0", + "icc_ap0r1", + "icc_ap0r2", + "icc_ap0r3", + "icc_ap1r0", + "icc_ap1r0_ns", + "icc_ap1r0_s", + "icc_ap1r1", + "icc_ap1r1_ns", + "icc_ap1r1_s", + "icc_ap1r2", + "icc_ap1r2_ns", + "icc_ap1r2_s", + "icc_ap1r3", + "icc_ap1r3_ns", + "icc_ap1r3_s", + "icc_asgi1r", + "icc_bpr0", + "icc_bpr1", + "icc_bpr1_ns", + "icc_bpr1_s", + "icc_ctlr", + "icc_ctlr_ns", + "icc_ctlr_s", + "icc_dir", + "icc_eoir0", + "icc_eoir1", + "icc_hppir0", + "icc_hppir1", + "icc_hsre", + "icc_iar0", + "icc_iar1", + "icc_igrpen0", + "icc_igrpen1", + "icc_igrpen1_ns", + "icc_igrpen1_s", + "icc_mctlr", + "icc_mgrpen1", + "icc_msre", + "icc_pmr", + "icc_rpr", + "icc_sgi0r", + "icc_sgi1r", + "icc_sre", + "icc_sre_ns", + "icc_sre_s", + + "ich_ap0r0", + "ich_ap0r1", + "ich_ap0r2", + "ich_ap0r3", + "ich_ap1r0", + "ich_ap1r1", + "ich_ap1r2", + "ich_ap1r3", + "ich_hcr", + "ich_vtr", + "ich_misr", + "ich_eisr", + "ich_elrsr", + "ich_vmcr", + "ich_lr0", + "ich_lr1", + "ich_lr2", + "ich_lr3", + "ich_lr4", + "ich_lr5", + "ich_lr6", + "ich_lr7", + "ich_lr8", + "ich_lr9", + "ich_lr10", + "ich_lr11", + "ich_lr12", + "ich_lr13", + "ich_lr14", + "ich_lr15", + "ich_lrc0", + "ich_lrc1", + "ich_lrc2", + "ich_lrc3", + "ich_lrc4", + "ich_lrc5", + "ich_lrc6", + "ich_lrc7", + "ich_lrc8", + "ich_lrc9", + "ich_lrc10", + "ich_lrc11", + "ich_lrc12", + "ich_lrc13", + "ich_lrc14", + "ich_lrc15", + "freeslot2", "num_phys_regs", diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc index 164c9658b..70622c328 100644 --- a/src/arch/arm/system.cc +++ b/src/arch/arm/system.cc @@ -48,6 +48,7 @@ #include "base/loader/object_file.hh" #include "base/loader/symtab.hh" #include "cpu/thread_context.hh" +#include "dev/arm/gic_v3.hh" #include "mem/fs_translating_port_proxy.hh" #include "mem/physical.hh" #include "sim/full_system.hh" @@ -63,6 +64,7 @@ ArmSystem::ArmSystem(Params *p) _haveVirtualization(p->have_virtualization), _haveCrypto(p->have_crypto), _genericTimer(nullptr), + _gic(nullptr), _resetAddr(p->auto_reset_addr ? (kernelEntry & loadAddrMask) + loadAddrOffset : p->reset_addr), @@ -136,6 +138,7 @@ ArmSystem::initState() const Params* p = params(); if (bootldr) { + bool isGICv3System = dynamic_cast<Gicv3 *>(getGIC()) != nullptr; bootldr->loadSections(physProxy); inform("Using bootloader at address %#x\n", bootldr->entryPoint()); @@ -143,15 +146,18 @@ ArmSystem::initState() // Put the address of the boot loader into r7 so we know // where to branch to after the reset fault // All other values needed by the boot loader to know what to do - if (!p->gic_cpu_addr || !p->flags_addr) - fatal("gic_cpu_addr && flags_addr must be set with bootloader\n"); + if (!p->flags_addr) + fatal("flags_addr must be set with bootloader\n"); + + if (!p->gic_cpu_addr && !isGICv3System) + fatal("gic_cpu_addr must be set with bootloader\n"); for (int i = 0; i < threadContexts.size(); i++) { if (!_highestELIs64) threadContexts[i]->setIntReg(3, (kernelEntry & loadAddrMask) + loadAddrOffset); - - threadContexts[i]->setIntReg(4, params()->gic_cpu_addr); + if (!isGICv3System) + threadContexts[i]->setIntReg(4, params()->gic_cpu_addr); threadContexts[i]->setIntReg(5, params()->flags_addr); } inform("Using kernel entry physical address at %#x\n", diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh index c6974609e..1a6a64fe7 100644 --- a/src/arch/arm/system.hh +++ b/src/arch/arm/system.hh @@ -54,6 +54,7 @@ #include "sim/system.hh" class GenericTimer; +class BaseGic; class ThreadContext; class ArmSystem : public System @@ -97,6 +98,7 @@ class ArmSystem : public System * Pointer to the Generic Timer wrapper. */ GenericTimer *_genericTimer; + BaseGic *_gic; /** * Reset address (ARMv8) @@ -192,9 +194,18 @@ class ArmSystem : public System _genericTimer = generic_timer; } + /** Sets the pointer to the GIC. */ + void setGIC(BaseGic *gic) + { + _gic = gic; + } + /** Get a pointer to the system's generic timer model */ GenericTimer *getGenericTimer() const { return _genericTimer; } + /** Get a pointer to the system's GIC */ + BaseGic *getGIC() const { return _gic; } + /** Returns true if the register width of the highest implemented exception * level is 64 bits (ARMv8) */ bool highestELIs64() const { return _highestELIs64; } |