diff options
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/SConscript | 1 | ||||
-rw-r--r-- | src/arch/arm/insts/branch.cc | 75 | ||||
-rw-r--r-- | src/arch/arm/insts/branch.hh | 7 |
3 files changed, 82 insertions, 1 deletions
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index 6ef445e10..d9b5661ca 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -49,6 +49,7 @@ if env['TARGET_ISA'] == 'arm': Dir('isa/formats') Source('decoder.cc') Source('faults.cc') + Source('insts/branch.cc') Source('insts/branch64.cc') Source('insts/data64.cc') Source('insts/macromem.cc') diff --git a/src/arch/arm/insts/branch.cc b/src/arch/arm/insts/branch.cc new file mode 100644 index 000000000..4de877e94 --- /dev/null +++ b/src/arch/arm/insts/branch.cc @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2018 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Giacomo Travaglini + */ + +#include "arch/arm/insts/branch.hh" + +#include "base/cprintf.hh" + +namespace ArmISA { + +std::string +BranchReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss, "", false); + printIntReg(ss, op1); + return ss.str(); +} + +std::string +BranchImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss, "", false); + printTarget(ss, pc + imm, symtab); + return ss.str(); +} + +std::string +BranchRegReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const +{ + std::stringstream ss; + printMnemonic(ss, "", false); + printIntReg(ss, op1); + ccprintf(ss, ", "); + printIntReg(ss, op2); + return ss.str(); +} + +} // namespace ArmISA diff --git a/src/arch/arm/insts/branch.hh b/src/arch/arm/insts/branch.hh index cc320dbff..9bc8cb8f7 100644 --- a/src/arch/arm/insts/branch.hh +++ b/src/arch/arm/insts/branch.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010,2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -58,6 +58,7 @@ class BranchImm : public PredOp PredOp(mnem, _machInst, __opClass), imm(_imm) {} + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; // Conditionally Branch to a target computed with an immediate @@ -85,6 +86,8 @@ class BranchReg : public PredOp IntRegIndex _op1) : PredOp(mnem, _machInst, __opClass), op1(_op1) {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; // Conditionally Branch to a target computed with a register @@ -113,6 +116,8 @@ class BranchRegReg : public PredOp IntRegIndex _op1, IntRegIndex _op2) : PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2) {} + + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; // Branch to a target computed with an immediate and a register |