summaryrefslogtreecommitdiff
path: root/src/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/ArmSystem.py1
-rw-r--r--src/arch/arm/isa_traits.hh3
2 files changed, 1 insertions, 3 deletions
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 872776c69..a93730867 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -32,4 +32,5 @@ from System import System
class ArmSystem(System):
type = 'ArmSystem'
+ load_addr_mask = 0xffffffff
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index d81981ff7..2744ec753 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -91,9 +91,6 @@ namespace ArmISA
const Addr KSeg0Base = ULL(0x80000000);
const Addr KSeg0Mask = ULL(0x1FFFFFFF);
- // For loading... XXX This maybe could be USegEnd?? --ali
- const Addr LoadAddrMask = ULL(0xffffffffff);
-
const unsigned VABits = 32;
const unsigned PABits = 32; // Is this correct?
const Addr VAddrImplMask = (ULL(1) << VABits) - 1;