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Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/fastmodel/iris/arm/thread_context.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.cc b/src/arch/arm/fastmodel/iris/arm/thread_context.cc index c48ade817..4ef879488 100644 --- a/src/arch/arm/fastmodel/iris/arm/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/arm/thread_context.cc @@ -190,6 +190,11 @@ const ArmISA::VecRegContainer & ArmThreadContext::readVecReg(const RegId ®_id) const { const RegIndex idx = reg_id.index(); + // Ignore accesses to registers which aren't architected. gem5 defines a + // few extra registers which it uses internally in the implementation of + // some instructions. + if (idx >= vecRegIds.size()) + return vecRegs.at(idx); ArmISA::VecRegContainer ® = vecRegs.at(idx); iris::ResourceReadResult result; |