1 files changed, 2 insertions, 7 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 97de97e6e..3b10f68a4 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -64,6 +64,7 @@ ISA::ISA(Params *p)
       _decoderFlavour(p->decoderFlavour),
       _vecRegRenameMode(Enums::Full),
       pmu(p->pmu),
+      haveGICv3CPUInterface(false),
       impdefAsNop(p->impdef_nop)
 {
     miscRegs[MISCREG_SCTLR_RST] = 0;
@@ -96,13 +97,6 @@ ISA::ISA(Params *p)
         physAddrRange = 32;  // dummy value
     }
 
-    // GICv3 CPU interface system registers are supported
-    haveGICv3CPUInterface = false;
-
-    if (system && dynamic_cast<Gicv3 *>(system->getGIC())) {
-        haveGICv3CPUInterface = true;
-    }
-
     // Initial rename mode depends on highestEL
     const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) =
         highestELIs64 ? Enums::Full : Enums::Elem;
@@ -388,6 +382,7 @@ ISA::startup(ThreadContext *tc)
     if (system) {
         Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
         if (gicv3) {
+            haveGICv3CPUInterface = true;
             gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
             gicv3CpuInterface->setISA(this);
         }