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-rw-r--r--src/arch/arm/isa/insts/data64.isa33
1 files changed, 15 insertions, 18 deletions
diff --git a/src/arch/arm/isa/insts/data64.isa b/src/arch/arm/isa/insts/data64.isa
index bb0334372..a2ffb9f5a 100644
--- a/src/arch/arm/isa/insts/data64.isa
+++ b/src/arch/arm/isa/insts/data64.isa
@@ -330,15 +330,26 @@ let {{
if (fault != NoFault) return fault;
'''
- mrsCode = '''
+ msr_check_code = '''
+ MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
+ flattenRegId(RegId(MiscRegClass, dest)).index();
+ CPSR cpsr = Cpsr;
+ ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
+ %s
+ ''' % (msrMrs64EnabledCheckCode % ('Write'),)
+
+ mrs_check_code = '''
MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
flattenRegId(RegId(MiscRegClass, op1)).index();
CPSR cpsr = Cpsr;
ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
%s
- XDest = MiscOp1_ud;
''' % (msrMrs64EnabledCheckCode % ('Read'),)
+
+ mrsCode = mrs_check_code + '''
+ XDest = MiscOp1_ud;
+ '''
mrsIop = InstObjParams("mrs", "Mrs64", "RegMiscRegImmOp64",
mrsCode,
["IsSerializeBefore"])
@@ -354,15 +365,9 @@ let {{
XDest = cpsr;
''')
- msrCode = '''
- MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
- flattenRegId(RegId(MiscRegClass, dest)).index();
- CPSR cpsr = Cpsr;
- ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
- %s
+ msrCode = msr_check_code + '''
MiscDest_ud = XOp1;
- ''' % (msrMrs64EnabledCheckCode % ('Write'),)
-
+ '''
msrIop = InstObjParams("msr", "Msr64", "MiscRegRegImmOp64",
msrCode,
["IsSerializeAfter", "IsNonSpeculative"])
@@ -378,14 +383,6 @@ let {{
CondCodesV = cpsr.v;
''')
- msr_check_code = '''
- MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
- flattenRegId(RegId(MiscRegClass, dest)).index();
- CPSR cpsr = Cpsr;
- ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
- %s
- ''' % (msrMrs64EnabledCheckCode % ('Write'),)
-
msrdczva_ea_code = msr_check_code
msrdczva_ea_code += '''