3 files changed, 9 insertions, 6 deletions
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 4a8e960d4..75945ad81 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2011, 2014, 2016-2018 ARM Limited
+ * Copyright (c) 2010-2011, 2014, 2016-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -61,6 +61,9 @@ const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
 using ArmISAInst::MaxInstDestRegs;
 using ArmISAInst::MaxMiscDestRegs;
 
+// Number of VecElem per Vector Register considering only pre-SVE
+// Advanced SIMD registers.
+constexpr unsigned NumVecElemPerNeonVecReg = 4;
 // Number of VecElem per Vector Register, computed based on the vector length
 constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords;
 
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 05adfeaed..ceb0ffafe 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -1,7 +1,7 @@
 /*
  * Copyright 2015 LabWare
  * Copyright 2014 Google Inc.
- * Copyright (c) 2010, 2013, 2016, 2018 ARM Limited
+ * Copyright (c) 2010, 2013, 2016, 2018-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -212,7 +212,7 @@ RemoteGDB::AArch64GdbRegCache::getRegs(ThreadContext *context)
     size_t base = 0;
     for (int i = 0; i < NumVecV8ArchRegs; i++) {
         auto v = (context->readVecReg(RegId(VecRegClass, i))).as<VecElem>();
-        for (size_t j = 0; j < NumVecElemPerVecReg; j++) {
+        for (size_t j = 0; j < NumVecElemPerNeonVecReg; j++) {
             r.v[base] = v[j];
             base++;
         }
@@ -241,7 +241,7 @@ RemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context) const
     for (int i = 0; i < NumVecV8ArchRegs; i++) {
         auto v = (context->getWritableVecReg(
                 RegId(VecRegClass, i))).as<VecElem>();
-        for (size_t j = 0; j < NumVecElemPerVecReg; j++) {
+        for (size_t j = 0; j < NumVecElemPerNeonVecReg; j++) {
             v[j] = r.v[base];
             base++;
         }
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index 3e4c5ef8d..e52ed663a 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -1,7 +1,7 @@
 /*
  * Copyright 2015 LabWare
  * Copyright 2014 Google, Inc.
- * Copyright (c) 2013, 2016, 2018 ARM Limited
+ * Copyright (c) 2013, 2016, 2018-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -97,7 +97,7 @@ class RemoteGDB : public BaseRemoteGDB
           uint64_t spx;
           uint64_t pc;
           uint32_t cpsr;
-          VecElem v[NumVecV8ArchRegs * NumVecElemPerVecReg];
+          VecElem v[NumVecV8ArchRegs * NumVecElemPerNeonVecReg];
           uint32_t fpsr;
           uint32_t fpcr;
         } M5_ATTR_PACKED r;