diff options
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa.cc | 3 | ||||
| -rw-r--r-- | src/arch/arm/table_walker.cc | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index a490e5fb7..44e4ff376 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -1653,6 +1653,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); } } + M5_FALLTHROUGH; case MISCREG_TTBR0: case MISCREG_TTBR1: { @@ -1666,12 +1667,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) } } } + M5_FALLTHROUGH; case MISCREG_SCTLR_EL1: { tc->getITBPtr()->invalidateMiscReg(); tc->getDTBPtr()->invalidateMiscReg(); setMiscRegNoEffect(misc_reg, newVal); } + M5_FALLTHROUGH; case MISCREG_CONTEXTIDR: case MISCREG_PRRR: case MISCREG_NMRR: diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 2d6664264..63b67f56a 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -1398,6 +1398,7 @@ TableWalker::memAttrsAArch64(ThreadContext *tc, TlbEntry &te, case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient warn_if(!attr_hi, "Unpredictable behavior"); + M5_FALLTHROUGH; case 0x4: // Device-nGnRE memory or // Normal memory, Inner Non-cacheable case 0x8: // Device-nGRE memory or |