summaryrefslogtreecommitdiff
path: root/src/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/tlb.cc2
-rw-r--r--src/arch/arm/tlb.hh2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 46056d07b..ed7e68039 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -1244,7 +1244,7 @@ TLB::translateComplete(const RequestPtr &req, ThreadContext *tc,
}
BaseMasterPort*
-TLB::getMasterPort()
+TLB::getTableWalkerMasterPort()
{
return &stage2Mmu->getPort();
}
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 637240abb..8ca176a82 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -401,7 +401,7 @@ class TLB : public BaseTLB
*
* @return A pointer to the walker master port
*/
- BaseMasterPort* getMasterPort() override;
+ BaseMasterPort* getTableWalkerMasterPort() override;
// Caching misc register values here.
// Writing to misc registers needs to invalidate them.