diff options
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa.cc | 5 | ||||
| -rw-r--r-- | src/arch/arm/isa.hh | 12 |
2 files changed, 16 insertions, 1 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 654608a08..cdc44cdb9 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -65,7 +65,8 @@ ISA::ISA(Params *p) _vecRegRenameMode(Enums::Full), pmu(p->pmu), haveGICv3CPUInterface(false), - impdefAsNop(p->impdef_nop) + impdefAsNop(p->impdef_nop), + afterStartup(false) { miscRegs[MISCREG_SCTLR_RST] = 0; @@ -406,6 +407,8 @@ ISA::startup(ThreadContext *tc) gicv3CpuInterface->setThreadContext(tc); } } + + afterStartup = true; } diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index 1931306f9..b4689d74e 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -105,6 +105,8 @@ namespace ArmISA */ bool impdefAsNop; + bool afterStartup; + /** MiscReg metadata **/ struct MiscRegLUTEntry { uint32_t lower; // Lower half mapped to this register @@ -706,6 +708,16 @@ namespace ArmISA Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; } + /** Getter for haveGICv3CPUInterface */ + bool haveGICv3CpuIfc() const + { + // haveGICv3CPUInterface is initialized at startup time, hence + // trying to read its value before the startup stage will lead + // to an error + assert(afterStartup); + return haveGICv3CPUInterface; + } + Enums::VecRegRenameMode vecRegRenameMode() const { |