diff options
Diffstat (limited to 'src/arch/generic/BaseTLB.py')
| -rw-r--r-- | src/arch/generic/BaseTLB.py | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py index 6a8a9727f..b98b99356 100644 --- a/src/arch/generic/BaseTLB.py +++ b/src/arch/generic/BaseTLB.py @@ -1,4 +1,5 @@ # Copyright (c) 2008 The Hewlett-Packard Development Company +# Copyright (c) 2018 Metempsy Technology Consulting # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -25,10 +26,15 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Gabe Black +# Ivan Pizarro -from m5.SimObject import SimObject +from m5.params import * +from MemObject import MemObject -class BaseTLB(SimObject): +class BaseTLB(MemObject): type = 'BaseTLB' abstract = True cxx_header = "arch/generic/tlb.hh" + # Ports to connect with other TLB levels + slave = VectorSlavePort("Port closer to the CPU side") + master = MasterPort("Port closer to memory side") |