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-rw-r--r--src/arch/generic/BaseTLB.py4
-rw-r--r--src/arch/generic/tlb.hh8
2 files changed, 5 insertions, 7 deletions
diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 688117a66..64531b9c5 100644
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -29,9 +29,9 @@
# Ivan Pizarro
from m5.params import *
-from m5.objects.MemObject import MemObject
+from m5.SimObject import SimObject
-class BaseTLB(MemObject):
+class BaseTLB(SimObject):
type = 'BaseTLB'
abstract = True
cxx_header = "arch/generic/tlb.hh"
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index ba07b1057..cd33ef4c9 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -44,18 +44,16 @@
#define __ARCH_GENERIC_TLB_HH__
#include "base/logging.hh"
-#include "mem/mem_object.hh"
#include "mem/request.hh"
+#include "sim/sim_object.hh"
class ThreadContext;
class BaseMasterPort;
-class BaseTLB : public MemObject
+class BaseTLB : public SimObject
{
protected:
- BaseTLB(const Params *p)
- : MemObject(p)
- {}
+ BaseTLB(const Params *p) : SimObject(p) {}
public: