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-rw-r--r--src/arch/hsail/insts/branch.hh14
-rw-r--r--src/arch/hsail/insts/decl.hh125
-rw-r--r--src/arch/hsail/insts/main.cc5
-rw-r--r--src/arch/hsail/insts/mem.cc63
-rw-r--r--src/arch/hsail/insts/mem.hh542
-rw-r--r--src/arch/hsail/insts/mem_impl.hh25
-rw-r--r--src/arch/hsail/insts/pseudo_inst.cc31
7 files changed, 403 insertions, 402 deletions
diff --git a/src/arch/hsail/insts/branch.hh b/src/arch/hsail/insts/branch.hh
index 45cd876ad..89bcc1277 100644
--- a/src/arch/hsail/insts/branch.hh
+++ b/src/arch/hsail/insts/branch.hh
@@ -59,16 +59,15 @@ namespace HsailISA
BrnInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
: HsailGPUStaticInst(obj, "brn")
{
- o_type = Enums::OT_BRANCH;
+ setFlag(Branch);
+ setFlag(UnconditionalJump);
width = ((Brig::BrigInstBr*)ib)->width;
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
target.init(op_offs, obj);
- o_type = Enums::OT_BRANCH;
}
uint32_t getTargetPc() override { return target.getTarget(0, 0); }
- bool unconditionalJumpInstruction() override { return true; }
bool isVectorRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
return target.isVectorRegister();
@@ -175,13 +174,12 @@ namespace HsailISA
CbrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
: HsailGPUStaticInst(obj, "cbr")
{
- o_type = Enums::OT_BRANCH;
+ setFlag(Branch);
width = ((Brig::BrigInstBr *)ib)->width;
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
cond.init(op_offs, obj);
op_offs = obj->getOperandPtr(ib->operands, 1);
target.init(op_offs, obj);
- o_type = Enums::OT_BRANCH;
}
uint32_t getTargetPc() override { return target.getTarget(0, 0); }
@@ -343,17 +341,15 @@ namespace HsailISA
BrInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj)
: HsailGPUStaticInst(obj, "br")
{
- o_type = Enums::OT_BRANCH;
+ setFlag(Branch);
+ setFlag(UnconditionalJump);
width.init(((Brig::BrigInstBr *)ib)->width, obj);
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
target.init(op_offs, obj);
- o_type = Enums::OT_BRANCH;
}
uint32_t getTargetPc() override { return target.getTarget(0, 0); }
- bool unconditionalJumpInstruction() override { return true; }
-
void execute(GPUDynInstPtr gpuDynInst) override;
bool isVectorRegister(int operandIndex) override {
assert(operandIndex >= 0 && operandIndex < getNumOperands());
diff --git a/src/arch/hsail/insts/decl.hh b/src/arch/hsail/insts/decl.hh
index 48e022ff7..94f23ac1f 100644
--- a/src/arch/hsail/insts/decl.hh
+++ b/src/arch/hsail/insts/decl.hh
@@ -38,11 +38,9 @@
#include <cmath>
-#include "arch/hsail/generic_types.hh"
#include "arch/hsail/insts/gpu_static_inst.hh"
#include "arch/hsail/operand.hh"
#include "debug/HSAIL.hh"
-#include "enums/OpType.hh"
#include "gpu-compute/gpu_dyn_inst.hh"
#include "gpu-compute/shader.hh"
@@ -127,6 +125,8 @@ namespace HsailISA
const char *opcode)
: HsailGPUStaticInst(obj, opcode)
{
+ setFlag(ALU);
+
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
dest.init(op_offs, obj);
@@ -240,6 +240,8 @@ namespace HsailISA
const char *opcode)
: HsailGPUStaticInst(obj, opcode)
{
+ setFlag(ALU);
+
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
dest.init(op_offs, obj);
@@ -414,6 +416,8 @@ namespace HsailISA
const BrigObject *obj, const char *opcode)
: HsailGPUStaticInst(obj, opcode)
{
+ setFlag(ALU);
+
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
dest.init(op_offs, obj);
@@ -818,6 +822,8 @@ namespace HsailISA
const BrigObject *obj, const char *_opcode)
: HsailGPUStaticInst(obj, _opcode)
{
+ setFlag(ALU);
+
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
dest.init(op_offs, obj);
@@ -874,7 +880,7 @@ namespace HsailISA
Ret(const Brig::BrigInstBase *ib, const BrigObject *obj)
: Base(ib, obj, "ret")
{
- o_type = Enums::OT_RET;
+ setFlag(GPUStaticInst::Return);
}
void execute(GPUDynInstPtr gpuDynInst);
@@ -889,7 +895,7 @@ namespace HsailISA
Barrier(const Brig::BrigInstBase *ib, const BrigObject *obj)
: Base(ib, obj, "barrier")
{
- o_type = Enums::OT_BARRIER;
+ setFlag(GPUStaticInst::MemBarrier);
assert(ib->base.kind == Brig::BRIG_KIND_INST_BR);
width = (uint8_t)((Brig::BrigInstBr*)ib)->width;
}
@@ -924,14 +930,105 @@ namespace HsailISA
memFenceMemOrder = (Brig::BrigMemoryOrder)
((Brig::BrigInstMemFence*)ib)->memoryOrder;
- // set o_type based on scopes
+ setFlag(MemoryRef);
+ setFlag(GPUStaticInst::MemFence);
+
+ switch (memFenceMemOrder) {
+ case Brig::BRIG_MEMORY_ORDER_NONE:
+ setFlag(NoOrder);
+ break;
+ case Brig::BRIG_MEMORY_ORDER_RELAXED:
+ setFlag(RelaxedOrder);
+ break;
+ case Brig::BRIG_MEMORY_ORDER_SC_ACQUIRE:
+ setFlag(Acquire);
+ break;
+ case Brig::BRIG_MEMORY_ORDER_SC_RELEASE:
+ setFlag(Release);
+ break;
+ case Brig::BRIG_MEMORY_ORDER_SC_ACQUIRE_RELEASE:
+ setFlag(AcquireRelease);
+ break;
+ default:
+ fatal("MemInst has bad BrigMemoryOrder\n");
+ }
+
+ // set inst flags based on scopes
if (memFenceScopeSegGlobal != Brig::BRIG_MEMORY_SCOPE_NONE &&
memFenceScopeSegGroup != Brig::BRIG_MEMORY_SCOPE_NONE) {
- o_type = Enums::OT_BOTH_MEMFENCE;
+ setFlag(GPUStaticInst::GlobalSegment);
+
+ /**
+ * A memory fence that has scope for
+ * both segments will use the global
+ * segment, and be executed in the
+ * global memory pipeline, therefore,
+ * we set the segment to match the
+ * global scope only
+ */
+ switch (memFenceScopeSegGlobal) {
+ case Brig::BRIG_MEMORY_SCOPE_NONE:
+ setFlag(NoScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_WORKITEM:
+ setFlag(WorkitemScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_WORKGROUP:
+ setFlag(WorkgroupScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_AGENT:
+ setFlag(DeviceScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_SYSTEM:
+ setFlag(SystemScope);
+ break;
+ default:
+ fatal("MemFence has bad global scope type\n");
+ }
} else if (memFenceScopeSegGlobal != Brig::BRIG_MEMORY_SCOPE_NONE) {
- o_type = Enums::OT_GLOBAL_MEMFENCE;
+ setFlag(GPUStaticInst::GlobalSegment);
+
+ switch (memFenceScopeSegGlobal) {
+ case Brig::BRIG_MEMORY_SCOPE_NONE:
+ setFlag(NoScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_WORKITEM:
+ setFlag(WorkitemScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_WORKGROUP:
+ setFlag(WorkgroupScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_AGENT:
+ setFlag(DeviceScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_SYSTEM:
+ setFlag(SystemScope);
+ break;
+ default:
+ fatal("MemFence has bad global scope type\n");
+ }
} else if (memFenceScopeSegGroup != Brig::BRIG_MEMORY_SCOPE_NONE) {
- o_type = Enums::OT_SHARED_MEMFENCE;
+ setFlag(GPUStaticInst::GroupSegment);
+
+ switch (memFenceScopeSegGroup) {
+ case Brig::BRIG_MEMORY_SCOPE_NONE:
+ setFlag(NoScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_WORKITEM:
+ setFlag(WorkitemScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_WORKGROUP:
+ setFlag(WorkgroupScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_AGENT:
+ setFlag(DeviceScope);
+ break;
+ case Brig::BRIG_MEMORY_SCOPE_SYSTEM:
+ setFlag(SystemScope);
+ break;
+ default:
+ fatal("MemFence has bad group scope type\n");
+ }
} else {
fatal("MemFence constructor: bad scope specifiers\n");
}
@@ -955,18 +1052,13 @@ namespace HsailISA
// etc.). We send a packet, tagged with the memory order and
// scope, and let the GPU coalescer handle it.
- if (o_type == Enums::OT_GLOBAL_MEMFENCE ||
- o_type == Enums::OT_BOTH_MEMFENCE) {
+ if (isGlobalSeg()) {
gpuDynInst->simdId = w->simdId;
gpuDynInst->wfSlotId = w->wfSlotId;
gpuDynInst->wfDynId = w->wfDynId;
gpuDynInst->kern_id = w->kernId;
gpuDynInst->cu_id = w->computeUnit->cu_id;
- gpuDynInst->memoryOrder =
- getGenericMemoryOrder(memFenceMemOrder);
- gpuDynInst->scope =
- getGenericMemoryScope(memFenceScopeSegGlobal);
gpuDynInst->useContinuation = false;
GlobalMemPipeline* gmp = &(w->computeUnit->globalMemoryPipe);
gmp->getGMReqFIFO().push(gpuDynInst);
@@ -975,10 +1067,10 @@ namespace HsailISA
w->rdGmReqsInPipe--;
w->memReqsInPipe--;
w->outstandingReqs++;
- } else if (o_type == Enums::OT_SHARED_MEMFENCE) {
+ } else if (isGroupSeg()) {
// no-op
} else {
- fatal("MemFence execute: bad o_type\n");
+ fatal("MemFence execute: bad op type\n");
}
}
};
@@ -1054,6 +1146,7 @@ namespace HsailISA
Call(const Brig::BrigInstBase *ib, const BrigObject *obj)
: HsailGPUStaticInst(obj, "call")
{
+ setFlag(ALU);
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
dest.init(op_offs, obj);
op_offs = obj->getOperandPtr(ib->operands, 1);
diff --git a/src/arch/hsail/insts/main.cc b/src/arch/hsail/insts/main.cc
index f1662430a..783689dd5 100644
--- a/src/arch/hsail/insts/main.cc
+++ b/src/arch/hsail/insts/main.cc
@@ -179,12 +179,13 @@ namespace HsailISA
w->computeUnit->cu_id, w->simdId, w->wfSlotId, w->wfDynId);
if (!refCount) {
+ setFlag(SystemScope);
+ setFlag(Release);
+ setFlag(GlobalSegment);
// Notify Memory System of Kernel Completion
// Kernel End = isKernel + isRelease
w->status = Wavefront::S_RETURNING;
GPUDynInstPtr local_mempacket = gpuDynInst;
- local_mempacket->memoryOrder = Enums::MEMORY_ORDER_SC_RELEASE;
- local_mempacket->scope = Enums::MEMORY_SCOPE_SYSTEM;
local_mempacket->useContinuation = false;
local_mempacket->simdId = w->simdId;
local_mempacket->wfSlotId = w->wfSlotId;
diff --git a/src/arch/hsail/insts/mem.cc b/src/arch/hsail/insts/mem.cc
index 97d4c902b..6a6928838 100644
--- a/src/arch/hsail/insts/mem.cc
+++ b/src/arch/hsail/insts/mem.cc
@@ -36,7 +36,6 @@
#include "arch/hsail/insts/mem.hh"
#include "arch/hsail/Brig.h"
-#include "enums/OpType.hh"
using namespace Brig;
@@ -44,68 +43,6 @@ namespace HsailISA
{
const char* atomicOpToString(BrigAtomicOperation brigOp);
- Enums::MemOpType
- brigAtomicToMemOpType(BrigOpcode brigOpCode, BrigAtomicOperation brigOp)
- {
- if (brigOpCode == Brig::BRIG_OPCODE_ATOMIC) {
- switch (brigOp) {
- case BRIG_ATOMIC_AND:
- return Enums::MO_AAND;
- case BRIG_ATOMIC_OR:
- return Enums::MO_AOR;
- case BRIG_ATOMIC_XOR:
- return Enums::MO_AXOR;
- case BRIG_ATOMIC_CAS:
- return Enums::MO_ACAS;
- case BRIG_ATOMIC_EXCH:
- return Enums::MO_AEXCH;
- case BRIG_ATOMIC_ADD:
- return Enums::MO_AADD;
- case BRIG_ATOMIC_WRAPINC:
- return Enums::MO_AINC;
- case BRIG_ATOMIC_WRAPDEC:
- return Enums::MO_ADEC;
- case BRIG_ATOMIC_MIN:
- return Enums::MO_AMIN;
- case BRIG_ATOMIC_MAX:
- return Enums::MO_AMAX;
- case BRIG_ATOMIC_SUB:
- return Enums::MO_ASUB;
- default:
- fatal("Bad BrigAtomicOperation code %d\n", brigOp);
- }
- } else if (brigOpCode == Brig::BRIG_OPCODE_ATOMICNORET) {
- switch (brigOp) {
- case BRIG_ATOMIC_AND:
- return Enums::MO_ANRAND;
- case BRIG_ATOMIC_OR:
- return Enums::MO_ANROR;
- case BRIG_ATOMIC_XOR:
- return Enums::MO_ANRXOR;
- case BRIG_ATOMIC_CAS:
- return Enums::MO_ANRCAS;
- case BRIG_ATOMIC_EXCH:
- return Enums::MO_ANREXCH;
- case BRIG_ATOMIC_ADD:
- return Enums::MO_ANRADD;
- case BRIG_ATOMIC_WRAPINC:
- return Enums::MO_ANRINC;
- case BRIG_ATOMIC_WRAPDEC:
- return Enums::MO_ANRDEC;
- case BRIG_ATOMIC_MIN:
- return Enums::MO_ANRMIN;
- case BRIG_ATOMIC_MAX:
- return Enums::MO_ANRMAX;
- case BRIG_ATOMIC_SUB:
- return Enums::MO_ANRSUB;
- default:
- fatal("Bad BrigAtomicOperation code %d\n", brigOp);
- }
- } else {
- fatal("Bad BrigAtomicOpcode %d\n", brigOpCode);
- }
- }
-
const char*
atomicOpToString(BrigAtomicOperation brigOp)
{
diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh
index acc8434be..e223c7cf5 100644
--- a/src/arch/hsail/insts/mem.hh
+++ b/src/arch/hsail/insts/mem.hh
@@ -96,6 +96,8 @@ namespace HsailISA
{
using namespace Brig;
+ setFlag(ALU);
+
unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
dest.init(op_offs, obj);
op_offs = obj->getOperandPtr(ib->operands, 1);
@@ -211,143 +213,119 @@ namespace HsailISA
Brig::BrigMemoryOrder memoryOrder;
Brig::BrigMemoryScope memoryScope;
unsigned int equivClass;
- bool isArgLoad()
- {
- return segment == Brig::BRIG_SEGMENT_KERNARG ||
- segment == Brig::BRIG_SEGMENT_ARG;
- }
- void
- initLd(const Brig::BrigInstBase *ib, const BrigObject *obj,
- const char *_opcode)
+
+ LdInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj,
+ const char *_opcode)
+ : HsailGPUStaticInst(obj, _opcode)
{
using namespace Brig;
- const BrigInstMem *ldst = (const BrigInstMem*)ib;
+ setFlag(MemoryRef);
+ setFlag(Load);
- segment = (BrigSegment)ldst->segment;
- memoryOrder = BRIG_MEMORY_ORDER_NONE;
- memoryScope = BRIG_MEMORY_SCOPE_NONE;
- equivClass = ldst->equivClass;
+ if (ib->opcode == BRIG_OPCODE_LD) {
+ const BrigInstMem *ldst = (const BrigInstMem*)ib;
- switch (segment) {
- case BRIG_SEGMENT_GLOBAL:
- o_type = Enums::OT_GLOBAL_READ;
- break;
+ segment = (BrigSegment)ldst->segment;
+ memoryOrder = BRIG_MEMORY_ORDER_NONE;
+ memoryScope = BRIG_MEMORY_SCOPE_NONE;
+ equivClass = ldst->equivClass;
- case BRIG_SEGMENT_GROUP:
- o_type = Enums::OT_SHARED_READ;
- break;
+ width = ldst->width;
+ unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
+ const Brig::BrigOperand *brigOp = obj->getOperand(op_offs);
+ if (brigOp->kind == BRIG_KIND_OPERAND_REGISTER)
+ dest.init(op_offs, obj);
- case BRIG_SEGMENT_PRIVATE:
- o_type = Enums::OT_PRIVATE_READ;
- break;
+ op_offs = obj->getOperandPtr(ib->operands, 1);
+ addr.init(op_offs, obj);
+ } else {
+ const BrigInstAtomic *at = (const BrigInstAtomic*)ib;
- case BRIG_SEGMENT_READONLY:
- o_type = Enums::OT_READONLY_READ;
- break;
+ segment = (BrigSegment)at->segment;
+ memoryOrder = (BrigMemoryOrder)at->memoryOrder;
+ memoryScope = (BrigMemoryScope)at->memoryScope;
+ equivClass = 0;
- case BRIG_SEGMENT_SPILL:
- o_type = Enums::OT_SPILL_READ;
- break;
+ width = BRIG_WIDTH_1;
+ unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
+ const Brig::BrigOperand *brigOp = obj->getOperand(op_offs);
- case BRIG_SEGMENT_FLAT:
- o_type = Enums::OT_FLAT_READ;
- break;
+ if (brigOp->kind == BRIG_KIND_OPERAND_REGISTER)
+ dest.init(op_offs, obj);
- case BRIG_SEGMENT_KERNARG:
- o_type = Enums::OT_KERN_READ;
- break;
+ op_offs = obj->getOperandPtr(ib->operands,1);
+ addr.init(op_offs, obj);
+ }
- case BRIG_SEGMENT_ARG:
- o_type = Enums::OT_ARG;
+ switch (memoryOrder) {
+ case BRIG_MEMORY_ORDER_NONE:
+ setFlag(NoOrder);
+ break;
+ case BRIG_MEMORY_ORDER_RELAXED:
+ setFlag(RelaxedOrder);
+ break;
+ case BRIG_MEMORY_ORDER_SC_ACQUIRE:
+ setFlag(Acquire);
+ break;
+ case BRIG_MEMORY_ORDER_SC_RELEASE:
+ setFlag(Release);
+ break;
+ case BRIG_MEMORY_ORDER_SC_ACQUIRE_RELEASE:
+ setFlag(AcquireRelease);
break;
-
default:
- panic("Ld: segment %d not supported\n", segment);
+ fatal("LdInst has bad memory order type\n");
}
- width = ldst->width;
- unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
- const Brig::BrigOperand *brigOp = obj->getOperand(op_offs);
- if (brigOp->kind == BRIG_KIND_OPERAND_REGISTER)
- dest.init(op_offs, obj);
-
- op_offs = obj->getOperandPtr(ib->operands, 1);
- addr.init(op_offs, obj);
- }
-
- void
- initAtomicLd(const Brig::BrigInstBase *ib, const BrigObject *obj,
- const char *_opcode)
- {
- using namespace Brig;
-
- const BrigInstAtomic *at = (const BrigInstAtomic*)ib;
-
- segment = (BrigSegment)at->segment;
- memoryOrder = (BrigMemoryOrder)at->memoryOrder;
- memoryScope = (BrigMemoryScope)at->memoryScope;
- equivClass = 0;
+ switch (memoryScope) {
+ case BRIG_MEMORY_SCOPE_NONE:
+ setFlag(NoScope);
+ break;
+ case BRIG_MEMORY_SCOPE_WORKITEM:
+ setFlag(WorkitemScope);
+ break;
+ case BRIG_MEMORY_SCOPE_WORKGROUP:
+ setFlag(WorkgroupScope);
+ break;
+ case BRIG_MEMORY_SCOPE_AGENT:
+ setFlag(DeviceScope);
+ break;
+ case BRIG_MEMORY_SCOPE_SYSTEM:
+ setFlag(SystemScope);
+ break;
+ default:
+ fatal("LdInst has bad memory scope type\n");
+ }
switch (segment) {
case BRIG_SEGMENT_GLOBAL:
- o_type = Enums::OT_GLOBAL_READ;
+ setFlag(GlobalSegment);
break;
-
case BRIG_SEGMENT_GROUP:
- o_type = Enums::OT_SHARED_READ;
+ setFlag(GroupSegment);
break;
-
case BRIG_SEGMENT_PRIVATE:
- o_type = Enums::OT_PRIVATE_READ;
+ setFlag(PrivateSegment);
break;
-
case BRIG_SEGMENT_READONLY:
- o_type = Enums::OT_READONLY_READ;
+ setFlag(ReadOnlySegment);
break;
-
case BRIG_SEGMENT_SPILL:
- o_type = Enums::OT_SPILL_READ;
+ setFlag(SpillSegment);
break;
-
case BRIG_SEGMENT_FLAT:
- o_type = Enums::OT_FLAT_READ;
+ setFlag(Flat);
break;
-
case BRIG_SEGMENT_KERNARG:
- o_type = Enums::OT_KERN_READ;
+ setFlag(KernArgSegment);
break;
-
case BRIG_SEGMENT_ARG:
- o_type = Enums::OT_ARG;
+ setFlag(ArgSegment);
break;
-
default:
panic("Ld: segment %d not supported\n", segment);
}
-
- width = BRIG_WIDTH_1;
- unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
- const Brig::BrigOperand *brigOp = obj->getOperand(op_offs);
-
- if (brigOp->kind == BRIG_KIND_OPERAND_REGISTER)
- dest.init(op_offs, obj);
-
- op_offs = obj->getOperandPtr(ib->operands,1);
- addr.init(op_offs, obj);
- }
-
- LdInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj,
- const char *_opcode)
- : HsailGPUStaticInst(obj, _opcode)
- {
- using namespace Brig;
-
- if (ib->opcode == BRIG_OPCODE_LD) {
- initLd(ib, obj, _opcode);
- } else {
- initAtomicLd(ib, obj, _opcode);
- }
}
int numSrcRegOperands() override
@@ -473,7 +451,7 @@ namespace HsailISA
if (gpuDynInst->exec_mask[i]) {
Addr vaddr = gpuDynInst->addr[i] + k * sizeof(c0);
- if (isLocalMem()) {
+ if (this->isLocalMem()) {
// load from shared memory
*d = gpuDynInst->wavefront()->ldsChunk->
read<c0>(vaddr);
@@ -488,8 +466,7 @@ namespace HsailISA
if (gpuDynInst->computeUnit()->shader->
separate_acquire_release &&
- gpuDynInst->memoryOrder ==
- Enums::MEMORY_ORDER_SC_ACQUIRE) {
+ gpuDynInst->isAcquire()) {
// if this load has acquire semantics,
// set the response continuation function
// to perform an Acquire request
@@ -520,10 +497,9 @@ namespace HsailISA
{
// after the load has complete and if the load has acquire
// semantics, issue an acquire request.
- if (!isLocalMem()) {
+ if (!this->isLocalMem()) {
if (gpuDynInst->computeUnit()->shader->separate_acquire_release
- && gpuDynInst->memoryOrder ==
- Enums::MEMORY_ORDER_SC_ACQUIRE) {
+ && gpuDynInst->isAcquire()) {
gpuDynInst->statusBitVector = VectorMask(1);
gpuDynInst->useContinuation = false;
// create request
@@ -537,12 +513,6 @@ namespace HsailISA
}
public:
- bool
- isLocalMem() const override
- {
- return this->segment == Brig::BRIG_SEGMENT_GROUP;
- }
-
bool isVectorRegister(int operandIndex) override
{
assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
@@ -731,128 +701,113 @@ namespace HsailISA
Brig::BrigMemoryOrder memoryOrder;
unsigned int equivClass;
- void
- initSt(const Brig::BrigInstBase *ib, const BrigObject *obj,
- const char *_opcode)
+ StInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj,
+ const char *_opcode)
+ : HsailGPUStaticInst(obj, _opcode)
{
using namespace Brig;
- const BrigInstMem *ldst = (const BrigInstMem*)ib;
+ setFlag(MemoryRef);
+ setFlag(Store);
- segment = (BrigSegment)ldst->segment;
- memoryOrder = BRIG_MEMORY_ORDER_NONE;
- memoryScope = BRIG_MEMORY_SCOPE_NONE;
- equivClass = ldst->equivClass;
+ if (ib->opcode == BRIG_OPCODE_ST) {
+ const BrigInstMem *ldst = (const BrigInstMem*)ib;
- switch (segment) {
- case BRIG_SEGMENT_GLOBAL:
- o_type = Enums::OT_GLOBAL_WRITE;
- break;
+ segment = (BrigSegment)ldst->segment;
+ memoryOrder = BRIG_MEMORY_ORDER_NONE;
+ memoryScope = BRIG_MEMORY_SCOPE_NONE;
+ equivClass = ldst->equivClass;
- case BRIG_SEGMENT_GROUP:
- o_type = Enums::OT_SHARED_WRITE;
- break;
+ unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
+ const BrigOperand *baseOp = obj->getOperand(op_offs);
- case BRIG_SEGMENT_PRIVATE:
- o_type = Enums::OT_PRIVATE_WRITE;
- break;
+ if ((baseOp->kind == BRIG_KIND_OPERAND_CONSTANT_BYTES) ||
+ (baseOp->kind == BRIG_KIND_OPERAND_REGISTER)) {
+ src.init(op_offs, obj);
+ }
- case BRIG_SEGMENT_READONLY:
- o_type = Enums::OT_READONLY_WRITE;
- break;
+ op_offs = obj->getOperandPtr(ib->operands, 1);
+ addr.init(op_offs, obj);
+ } else {
+ const BrigInstAtomic *at = (const BrigInstAtomic*)ib;
- case BRIG_SEGMENT_SPILL:
- o_type = Enums::OT_SPILL_WRITE;
- break;
+ segment = (BrigSegment)at->segment;
+ memoryScope = (BrigMemoryScope)at->memoryScope;
+ memoryOrder = (BrigMemoryOrder)at->memoryOrder;
+ equivClass = 0;
- case BRIG_SEGMENT_FLAT:
- o_type = Enums::OT_FLAT_WRITE;
- break;
+ unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
+ addr.init(op_offs, obj);
- case BRIG_SEGMENT_ARG:
- o_type = Enums::OT_ARG;
- break;
+ op_offs = obj->getOperandPtr(ib->operands, 1);
+ src.init(op_offs, obj);
+ }
+ switch (memoryOrder) {
+ case BRIG_MEMORY_ORDER_NONE:
+ setFlag(NoOrder);
+ break;
+ case BRIG_MEMORY_ORDER_RELAXED:
+ setFlag(RelaxedOrder);
+ break;
+ case BRIG_MEMORY_ORDER_SC_ACQUIRE:
+ setFlag(Acquire);
+ break;
+ case BRIG_MEMORY_ORDER_SC_RELEASE:
+ setFlag(Release);
+ break;
+ case BRIG_MEMORY_ORDER_SC_ACQUIRE_RELEASE:
+ setFlag(AcquireRelease);
+ break;
default:
- panic("St: segment %d not supported\n", segment);
+ fatal("StInst has bad memory order type\n");
}
- unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
- const BrigOperand *baseOp = obj->getOperand(op_offs);
-
- if ((baseOp->kind == BRIG_KIND_OPERAND_CONSTANT_BYTES) ||
- (baseOp->kind == BRIG_KIND_OPERAND_REGISTER)) {
- src.init(op_offs, obj);
+ switch (memoryScope) {
+ case BRIG_MEMORY_SCOPE_NONE:
+ setFlag(NoScope);
+ break;
+ case BRIG_MEMORY_SCOPE_WORKITEM:
+ setFlag(WorkitemScope);
+ break;
+ case BRIG_MEMORY_SCOPE_WORKGROUP:
+ setFlag(WorkgroupScope);
+ break;
+ case BRIG_MEMORY_SCOPE_AGENT:
+ setFlag(DeviceScope);
+ break;
+ case BRIG_MEMORY_SCOPE_SYSTEM:
+ setFlag(SystemScope);
+ break;
+ default:
+ fatal("StInst has bad memory scope type\n");
}
- op_offs = obj->getOperandPtr(ib->operands, 1);
- addr.init(op_offs, obj);
- }
-
- void
- initAtomicSt(const Brig::BrigInstBase *ib, const BrigObject *obj,
- const char *_opcode)
- {
- using namespace Brig;
-
- const BrigInstAtomic *at = (const BrigInstAtomic*)ib;
-
- segment = (BrigSegment)at->segment;
- memoryScope = (BrigMemoryScope)at->memoryScope;
- memoryOrder = (BrigMemoryOrder)at->memoryOrder;
- equivClass = 0;
-
switch (segment) {
case BRIG_SEGMENT_GLOBAL:
- o_type = Enums::OT_GLOBAL_WRITE;
+ setFlag(GlobalSegment);
break;
-
case BRIG_SEGMENT_GROUP:
- o_type = Enums::OT_SHARED_WRITE;
+ setFlag(GroupSegment);
break;
-
case BRIG_SEGMENT_PRIVATE:
- o_type = Enums::OT_PRIVATE_WRITE;
+ setFlag(PrivateSegment);
break;
-
case BRIG_SEGMENT_READONLY:
- o_type = Enums::OT_READONLY_WRITE;
+ setFlag(ReadOnlySegment);
break;
-
case BRIG_SEGMENT_SPILL:
- o_type = Enums::OT_SPILL_WRITE;
+ setFlag(SpillSegment);
break;
-
case BRIG_SEGMENT_FLAT:
- o_type = Enums::OT_FLAT_WRITE;
+ setFlag(Flat);
break;
-
case BRIG_SEGMENT_ARG:
- o_type = Enums::OT_ARG;
+ setFlag(ArgSegment);
break;
-
default:
panic("St: segment %d not supported\n", segment);
}
-
- unsigned op_offs = obj->getOperandPtr(ib->operands, 0);
- addr.init(op_offs, obj);
-
- op_offs = obj->getOperandPtr(ib->operands, 1);
- src.init(op_offs, obj);
- }
-
- StInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj,
- const char *_opcode)
- : HsailGPUStaticInst(obj, _opcode)
- {
- using namespace Brig;
-
- if (ib->opcode == BRIG_OPCODE_ST) {
- initSt(ib, obj, _opcode);
- } else {
- initAtomicSt(ib, obj, _opcode);
- }
}
int numDstRegOperands() override { return 0; }
@@ -964,10 +919,9 @@ namespace HsailISA
{
// before performing a store, check if this store has
// release semantics, and if so issue a release first
- if (!isLocalMem()) {
+ if (!this->isLocalMem()) {
if (gpuDynInst->computeUnit()->shader->separate_acquire_release
- && gpuDynInst->memoryOrder ==
- Enums::MEMORY_ORDER_SC_RELEASE) {
+ && gpuDynInst->isRelease()) {
gpuDynInst->statusBitVector = VectorMask(1);
gpuDynInst->execContinuation = &GPUStaticInst::execSt;
@@ -987,12 +941,6 @@ namespace HsailISA
execSt(gpuDynInst);
}
- bool
- isLocalMem() const override
- {
- return this->segment == Brig::BRIG_SEGMENT_GROUP;
- }
-
private:
// execSt may be called through a continuation
// if the store had release semantics. see comment for
@@ -1020,7 +968,7 @@ namespace HsailISA
if (gpuDynInst->exec_mask[i]) {
Addr vaddr = gpuDynInst->addr[i] + k * sizeof(c0);
- if (isLocalMem()) {
+ if (this->isLocalMem()) {
//store to shared memory
gpuDynInst->wavefront()->ldsChunk->write<c0>(vaddr,
*d);
@@ -1166,9 +1114,6 @@ namespace HsailISA
}
}
- Enums::MemOpType brigAtomicToMemOpType(Brig::BrigOpcode brigOpCode,
- Brig::BrigAtomicOperation brigOp);
-
template<typename OperandType, typename AddrOperandType, int NumSrcOperands,
bool HasDst>
class AtomicInstBase : public HsailGPUStaticInst
@@ -1183,7 +1128,6 @@ namespace HsailISA
Brig::BrigAtomicOperation atomicOperation;
Brig::BrigMemoryScope memoryScope;
Brig::BrigOpcode opcode;
- Enums::MemOpType opType;
AtomicInstBase(const Brig::BrigInstBase *ib, const BrigObject *obj,
const char *_opcode)
@@ -1198,21 +1142,106 @@ namespace HsailISA
memoryOrder = (BrigMemoryOrder)at->memoryOrder;
atomicOperation = (BrigAtomicOperation)at->atomicOperation;
opcode = (BrigOpcode)ib->opcode;
- opType = brigAtomicToMemOpType(opcode, atomicOperation);
+
+ assert(opcode == Brig::BRIG_OPCODE_ATOMICNORET ||
+ opcode == Brig::BRIG_OPCODE_ATOMIC);
+
+ setFlag(MemoryRef);
+
+ if (opcode == Brig::BRIG_OPCODE_ATOMIC) {
+ setFlag(AtomicReturn);
+ } else {
+ setFlag(AtomicNoReturn);
+ }
+
+ switch (memoryOrder) {
+ case BRIG_MEMORY_ORDER_NONE:
+ setFlag(NoOrder);
+ break;
+ case BRIG_MEMORY_ORDER_RELAXED:
+ setFlag(RelaxedOrder);
+ break;
+ case BRIG_MEMORY_ORDER_SC_ACQUIRE:
+ setFlag(Acquire);
+ break;
+ case BRIG_MEMORY_ORDER_SC_RELEASE:
+ setFlag(Release);
+ break;
+ case BRIG_MEMORY_ORDER_SC_ACQUIRE_RELEASE:
+ setFlag(AcquireRelease);
+ break;
+ default:
+ fatal("AtomicInst has bad memory order type\n");
+ }
+
+ switch (memoryScope) {
+ case BRIG_MEMORY_SCOPE_NONE:
+ setFlag(NoScope);
+ break;
+ case BRIG_MEMORY_SCOPE_WORKITEM:
+ setFlag(WorkitemScope);
+ break;
+ case BRIG_MEMORY_SCOPE_WORKGROUP:
+ setFlag(WorkgroupScope);
+ break;
+ case BRIG_MEMORY_SCOPE_AGENT:
+ setFlag(DeviceScope);
+ break;
+ case BRIG_MEMORY_SCOPE_SYSTEM:
+ setFlag(SystemScope);
+ break;
+ default:
+ fatal("AtomicInst has bad memory scope type\n");
+ }
+
+ switch (atomicOperation) {
+ case Brig::BRIG_ATOMIC_AND:
+ setFlag(AtomicAnd);
+ break;
+ case Brig::BRIG_ATOMIC_OR:
+ setFlag(AtomicOr);
+ break;
+ case Brig::BRIG_ATOMIC_XOR:
+ setFlag(AtomicXor);
+ break;
+ case Brig::BRIG_ATOMIC_CAS:
+ setFlag(AtomicCAS);
+ break;
+ case Brig::BRIG_ATOMIC_EXCH:
+ setFlag(AtomicExch);
+ break;
+ case Brig::BRIG_ATOMIC_ADD:
+ setFlag(AtomicAdd);
+ break;
+ case Brig::BRIG_ATOMIC_WRAPINC:
+ setFlag(AtomicInc);
+ break;
+ case Brig::BRIG_ATOMIC_WRAPDEC:
+ setFlag(AtomicDec);
+ break;
+ case Brig::BRIG_ATOMIC_MIN:
+ setFlag(AtomicMin);
+ break;
+ case Brig::BRIG_ATOMIC_MAX:
+ setFlag(AtomicMax);
+ break;
+ case Brig::BRIG_ATOMIC_SUB:
+ setFlag(AtomicSub);
+ break;
+ default:
+ fatal("Bad BrigAtomicOperation code %d\n", atomicOperation);
+ }
switch (segment) {
case BRIG_SEGMENT_GLOBAL:
- o_type = Enums::OT_GLOBAL_ATOMIC;
+ setFlag(GlobalSegment);
break;
-
case BRIG_SEGMENT_GROUP:
- o_type = Enums::OT_SHARED_ATOMIC;
+ setFlag(GroupSegment);
break;
-
case BRIG_SEGMENT_FLAT:
- o_type = Enums::OT_FLAT_ATOMIC;
+ setFlag(Flat);
break;
-
default:
panic("Atomic: segment %d not supported\n", segment);
}
@@ -1354,11 +1383,10 @@ namespace HsailISA
{
// before doing the RMW, check if this atomic has
// release semantics, and if so issue a release first
- if (!isLocalMem()) {
+ if (!this->isLocalMem()) {
if (gpuDynInst->computeUnit()->shader->separate_acquire_release
- && (gpuDynInst->memoryOrder ==
- Enums::MEMORY_ORDER_SC_RELEASE || gpuDynInst->memoryOrder ==
- Enums::MEMORY_ORDER_SC_ACQUIRE_RELEASE)) {
+ && (gpuDynInst->isRelease()
+ || gpuDynInst->isAcquireRelease())) {
gpuDynInst->statusBitVector = VectorMask(1);
@@ -1383,12 +1411,6 @@ namespace HsailISA
void execute(GPUDynInstPtr gpuDynInst) override;
- bool
- isLocalMem() const override
- {
- return this->segment == Brig::BRIG_SEGMENT_GROUP;
- }
-
private:
// execAtomic may be called through a continuation
// if the RMW had release semantics. see comment for
@@ -1408,72 +1430,48 @@ namespace HsailISA
if (gpuDynInst->exec_mask[i]) {
Addr vaddr = gpuDynInst->addr[i];
- if (isLocalMem()) {
+ if (this->isLocalMem()) {
Wavefront *wavefront = gpuDynInst->wavefront();
*d = wavefront->ldsChunk->read<c0>(vaddr);
- switch (this->opType) {
- case Enums::MO_AADD:
- case Enums::MO_ANRADD:
+ if (this->isAtomicAdd()) {
wavefront->ldsChunk->write<c0>(vaddr,
wavefront->ldsChunk->read<c0>(vaddr) + (*e));
- break;
- case Enums::MO_ASUB:
- case Enums::MO_ANRSUB:
+ } else if (this->isAtomicSub()) {
wavefront->ldsChunk->write<c0>(vaddr,
wavefront->ldsChunk->read<c0>(vaddr) - (*e));
- break;
- case Enums::MO_AMAX:
- case Enums::MO_ANRMAX:
+ } else if (this->isAtomicMax()) {
wavefront->ldsChunk->write<c0>(vaddr,
std::max(wavefront->ldsChunk->read<c0>(vaddr),
(*e)));
- break;
- case Enums::MO_AMIN:
- case Enums::MO_ANRMIN:
+ } else if (this->isAtomicMin()) {
wavefront->ldsChunk->write<c0>(vaddr,
std::min(wavefront->ldsChunk->read<c0>(vaddr),
(*e)));
- break;
- case Enums::MO_AAND:
- case Enums::MO_ANRAND:
+ } else if (this->isAtomicAnd()) {
wavefront->ldsChunk->write<c0>(vaddr,
wavefront->ldsChunk->read<c0>(vaddr) & (*e));
- break;
- case Enums::MO_AOR:
- case Enums::MO_ANROR:
+ } else if (this->isAtomicOr()) {
wavefront->ldsChunk->write<c0>(vaddr,
wavefront->ldsChunk->read<c0>(vaddr) | (*e));
- break;
- case Enums::MO_AXOR:
- case Enums::MO_ANRXOR:
+ } else if (this->isAtomicXor()) {
wavefront->ldsChunk->write<c0>(vaddr,
wavefront->ldsChunk->read<c0>(vaddr) ^ (*e));
- break;
- case Enums::MO_AINC:
- case Enums::MO_ANRINC:
+ } else if (this->isAtomicInc()) {
wavefront->ldsChunk->write<c0>(vaddr,
wavefront->ldsChunk->read<c0>(vaddr) + 1);
- break;
- case Enums::MO_ADEC:
- case Enums::MO_ANRDEC:
+ } else if (this->isAtomicDec()) {
wavefront->ldsChunk->write<c0>(vaddr,
wavefront->ldsChunk->read<c0>(vaddr) - 1);
- break;
- case Enums::MO_AEXCH:
- case Enums::MO_ANREXCH:
+ } else if (this->isAtomicExch()) {
wavefront->ldsChunk->write<c0>(vaddr, (*e));
- break;
- case Enums::MO_ACAS:
- case Enums::MO_ANRCAS:
+ } else if (this->isAtomicCAS()) {
wavefront->ldsChunk->write<c0>(vaddr,
(wavefront->ldsChunk->read<c0>(vaddr) == (*e)) ?
(*f) : wavefront->ldsChunk->read<c0>(vaddr));
- break;
- default:
+ } else {
fatal("Unrecognized or invalid HSAIL atomic op "
"type.\n");
- break;
}
} else {
Request *req =
@@ -1481,7 +1479,7 @@ namespace HsailISA
gpuDynInst->computeUnit()->masterId(),
0, gpuDynInst->wfDynId,
gpuDynInst->makeAtomicOpFunctor<c0>(e,
- f, this->opType));
+ f));
gpuDynInst->setRequestFlags(req);
PacketPtr pkt = new Packet(req, MemCmd::SwapReq);
@@ -1489,8 +1487,7 @@ namespace HsailISA
if (gpuDynInst->computeUnit()->shader->
separate_acquire_release &&
- (gpuDynInst->memoryOrder ==
- Enums::MEMORY_ORDER_SC_ACQUIRE)) {
+ (gpuDynInst->isAcquire())) {
// if this atomic has acquire semantics,
// schedule the continuation to perform an
// acquire after the RMW completes
@@ -1523,10 +1520,9 @@ namespace HsailISA
{
// after performing the RMW, check to see if this instruction
// has acquire semantics, and if so, issue an acquire
- if (!isLocalMem()) {
+ if (!this->isLocalMem()) {
if (gpuDynInst->computeUnit()->shader->separate_acquire_release
- && gpuDynInst->memoryOrder ==
- Enums::MEMORY_ORDER_SC_ACQUIRE) {
+ && gpuDynInst->isAcquire()) {
gpuDynInst->statusBitVector = VectorMask(1);
// the request will be finished when
diff --git a/src/arch/hsail/insts/mem_impl.hh b/src/arch/hsail/insts/mem_impl.hh
index e3529f914..c175f2782 100644
--- a/src/arch/hsail/insts/mem_impl.hh
+++ b/src/arch/hsail/insts/mem_impl.hh
@@ -33,7 +33,6 @@
* Author: Steve Reinhardt
*/
-#include "arch/hsail/generic_types.hh"
#include "gpu-compute/hsail_code.hh"
// defined in code.cc, but not worth sucking in all of code.h for this
@@ -215,16 +214,12 @@ namespace HsailISA
this->addr.calcVector(w, m->addr);
- m->m_op = Enums::MO_LD;
m->m_type = MemDataType::memType;
m->v_type = DestDataType::vgprType;
m->exec_mask = w->execMask();
m->statusBitVector = 0;
m->equiv = this->equivClass;
- m->memoryOrder = getGenericMemoryOrder(this->memoryOrder);
-
- m->scope = getGenericMemoryScope(this->memoryScope);
if (num_dest_operands == 1) {
m->dst_reg = this->dest.regIndex();
@@ -245,7 +240,6 @@ namespace HsailISA
switch (this->segment) {
case Brig::BRIG_SEGMENT_GLOBAL:
- m->s_type = SEG_GLOBAL;
m->pipeId = GLBMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(1));
@@ -276,7 +270,6 @@ namespace HsailISA
case Brig::BRIG_SEGMENT_SPILL:
assert(num_dest_operands == 1);
- m->s_type = SEG_SPILL;
m->pipeId = GLBMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(1));
{
@@ -301,7 +294,6 @@ namespace HsailISA
break;
case Brig::BRIG_SEGMENT_GROUP:
- m->s_type = SEG_SHARED;
m->pipeId = LDSMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(24));
w->computeUnit->localMemoryPipe.getLMReqFIFO().push(m);
@@ -310,7 +302,6 @@ namespace HsailISA
break;
case Brig::BRIG_SEGMENT_READONLY:
- m->s_type = SEG_READONLY;
m->pipeId = GLBMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(1));
@@ -327,7 +318,6 @@ namespace HsailISA
break;
case Brig::BRIG_SEGMENT_PRIVATE:
- m->s_type = SEG_PRIVATE;
m->pipeId = GLBMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(1));
{
@@ -408,7 +398,6 @@ namespace HsailISA
}
}
- m->m_op = Enums::MO_ST;
m->m_type = OperationType::memType;
m->v_type = OperationType::vgprType;
@@ -421,10 +410,6 @@ namespace HsailISA
m->n_reg = num_src_operands;
}
- m->memoryOrder = getGenericMemoryOrder(this->memoryOrder);
-
- m->scope = getGenericMemoryScope(this->memoryScope);
-
m->simdId = w->simdId;
m->wfSlotId = w->wfSlotId;
m->wfDynId = w->wfDynId;
@@ -434,7 +419,6 @@ namespace HsailISA
switch (this->segment) {
case Brig::BRIG_SEGMENT_GLOBAL:
- m->s_type = SEG_GLOBAL;
m->pipeId = GLBMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(1));
@@ -463,7 +447,6 @@ namespace HsailISA
case Brig::BRIG_SEGMENT_SPILL:
assert(num_src_operands == 1);
- m->s_type = SEG_SPILL;
m->pipeId = GLBMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(1));
{
@@ -483,7 +466,6 @@ namespace HsailISA
break;
case Brig::BRIG_SEGMENT_GROUP:
- m->s_type = SEG_SHARED;
m->pipeId = LDSMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(24));
w->computeUnit->localMemoryPipe.getLMReqFIFO().push(m);
@@ -492,7 +474,6 @@ namespace HsailISA
break;
case Brig::BRIG_SEGMENT_PRIVATE:
- m->s_type = SEG_PRIVATE;
m->pipeId = GLBMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(1));
{
@@ -586,7 +567,6 @@ namespace HsailISA
assert(NumSrcOperands <= 2);
- m->m_op = this->opType;
m->m_type = DataType::memType;
m->v_type = DataType::vgprType;
@@ -594,9 +574,6 @@ namespace HsailISA
m->statusBitVector = 0;
m->equiv = 0; // atomics don't have an equivalence class operand
m->n_reg = 1;
- m->memoryOrder = getGenericMemoryOrder(this->memoryOrder);
-
- m->scope = getGenericMemoryScope(this->memoryScope);
if (HasDst) {
m->dst_reg = this->dest.regIndex();
@@ -611,7 +588,6 @@ namespace HsailISA
switch (this->segment) {
case Brig::BRIG_SEGMENT_GLOBAL:
- m->s_type = SEG_GLOBAL;
m->latency.set(w->computeUnit->shader->ticks(64));
m->pipeId = GLBMEM_PIPE;
@@ -623,7 +599,6 @@ namespace HsailISA
break;
case Brig::BRIG_SEGMENT_GROUP:
- m->s_type = SEG_SHARED;
m->pipeId = LDSMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(24));
w->computeUnit->localMemoryPipe.getLMReqFIFO().push(m);
diff --git a/src/arch/hsail/insts/pseudo_inst.cc b/src/arch/hsail/insts/pseudo_inst.cc
index 2bfc5aaad..bfffb7d8f 100644
--- a/src/arch/hsail/insts/pseudo_inst.cc
+++ b/src/arch/hsail/insts/pseudo_inst.cc
@@ -627,8 +627,12 @@ namespace HsailISA
((int*)m->a_data)[lane] = src1.get<int>(w, lane, 3);
}
- m->m_op = brigAtomicToMemOpType(Brig::BRIG_OPCODE_ATOMICNORET,
- Brig::BRIG_ATOMIC_ADD);
+ setFlag(AtomicNoReturn);
+ setFlag(AtomicAdd);
+ setFlag(NoScope);
+ setFlag(NoOrder);
+ setFlag(GlobalSegment);
+
m->m_type = U32::memType;
m->v_type = U32::vgprType;
@@ -636,15 +640,12 @@ namespace HsailISA
m->statusBitVector = 0;
m->equiv = 0; // atomics don't have an equivalence class operand
m->n_reg = 1;
- m->memoryOrder = Enums::MEMORY_ORDER_NONE;
- m->scope = Enums::MEMORY_SCOPE_NONE;
m->simdId = w->simdId;
m->wfSlotId = w->wfSlotId;
m->wfDynId = w->wfDynId;
m->latency.init(&w->computeUnit->shader->tick_cnt);
- m->s_type = SEG_GLOBAL;
m->pipeId = GLBMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(64));
w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
@@ -666,8 +667,12 @@ namespace HsailISA
((int*)m->a_data)[lane] = src1.get<int>(w, lane, 1);
}
- m->m_op = brigAtomicToMemOpType(Brig::BRIG_OPCODE_ATOMICNORET,
- Brig::BRIG_ATOMIC_ADD);
+ setFlag(AtomicNoReturn);
+ setFlag(AtomicAdd);
+ setFlag(NoScope);
+ setFlag(NoOrder);
+ setFlag(GlobalSegment);
+
m->m_type = U32::memType;
m->v_type = U32::vgprType;
@@ -675,15 +680,12 @@ namespace HsailISA
m->statusBitVector = 0;
m->equiv = 0; // atomics don't have an equivalence class operand
m->n_reg = 1;
- m->memoryOrder = Enums::MEMORY_ORDER_NONE;
- m->scope = Enums::MEMORY_SCOPE_NONE;
m->simdId = w->simdId;
m->wfSlotId = w->wfSlotId;
m->wfDynId = w->wfDynId;
m->latency.init(&w->computeUnit->shader->tick_cnt);
- m->s_type = SEG_GLOBAL;
m->pipeId = GLBMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(64));
w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
@@ -702,7 +704,11 @@ namespace HsailISA
// calculate the address
calcAddr(w, m);
- m->m_op = Enums::MO_LD;
+ setFlag(Load);
+ setFlag(NoScope);
+ setFlag(NoOrder);
+ setFlag(GlobalSegment);
+
m->m_type = U32::memType; //MemDataType::memType;
m->v_type = U32::vgprType; //DestDataType::vgprType;
@@ -710,8 +716,6 @@ namespace HsailISA
m->statusBitVector = 0;
m->equiv = 0;
m->n_reg = 1;
- m->memoryOrder = Enums::MEMORY_ORDER_NONE;
- m->scope = Enums::MEMORY_SCOPE_NONE;
// FIXME
//m->dst_reg = this->dest.regIndex();
@@ -721,7 +725,6 @@ namespace HsailISA
m->wfDynId = w->wfDynId;
m->latency.init(&w->computeUnit->shader->tick_cnt);
- m->s_type = SEG_GLOBAL;
m->pipeId = GLBMEM_PIPE;
m->latency.set(w->computeUnit->shader->ticks(1));
w->computeUnit->globalMemoryPipe.getGMReqFIFO().push(m);
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-10 20:54:10 +0000