diff options
Diffstat (limited to 'src/arch/hsail')
| -rwxr-xr-x | src/arch/hsail/gen.py | 2 | ||||
| -rw-r--r-- | src/arch/hsail/insts/decl.hh | 12 | ||||
| -rw-r--r-- | src/arch/hsail/insts/mem.hh | 2 |
3 files changed, 8 insertions, 8 deletions
diff --git a/src/arch/hsail/gen.py b/src/arch/hsail/gen.py index f2996019b..bb369fd10 100755 --- a/src/arch/hsail/gen.py +++ b/src/arch/hsail/gen.py @@ -584,7 +584,7 @@ def gen(brig_opcode, types=None, expr=None, base_class='ArithInst', else: decoder_code(decode_case_prolog) if not type2_info: - if is_store == False: + if not is_store: # single list of types, to basic one-level decode for type_name in types: full_class_name = '%s<%s>' % (class_name, type_name.upper()) diff --git a/src/arch/hsail/insts/decl.hh b/src/arch/hsail/insts/decl.hh index e2da501b9..90609c365 100644 --- a/src/arch/hsail/insts/decl.hh +++ b/src/arch/hsail/insts/decl.hh @@ -189,7 +189,7 @@ namespace HsailISA int numSrcRegOperands() { int operands = 0; for (int i = 0; i < NumSrcOperands; i++) { - if (src[i].isVectorRegister() == true) { + if (src[i].isVectorRegister()) { operands++; } } @@ -325,13 +325,13 @@ namespace HsailISA int numSrcRegOperands() { int operands = 0; - if (src0.isVectorRegister() == true) { + if (src0.isVectorRegister()) { operands++; } - if (src1.isVectorRegister() == true) { + if (src1.isVectorRegister()) { operands++; } - if (src2.isVectorRegister() == true) { + if (src2.isVectorRegister()) { operands++; } return operands; @@ -485,10 +485,10 @@ namespace HsailISA int numSrcRegOperands() { int operands = 0; - if (src0.isVectorRegister() == true) { + if (src0.isVectorRegister()) { operands++; } - if (src1.isVectorRegister() == true) { + if (src1.isVectorRegister()) { operands++; } return operands; diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh index d3ce76dee..c3b3bd4f9 100644 --- a/src/arch/hsail/insts/mem.hh +++ b/src/arch/hsail/insts/mem.hh @@ -1239,7 +1239,7 @@ namespace HsailISA { int operands = 0; for (int i = 0; i < NumSrcOperands; i++) { - if (src[i].isVectorRegister() == true) { + if (src[i].isVectorRegister()) { operands++; } } |